mbox series

[v4,0/3] riscv: Per-thread envcfg CSR support

Message ID 20240814081126.956287-1-samuel.holland@sifive.com (mailing list archive)
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Series riscv: Per-thread envcfg CSR support | expand

Message

Samuel Holland Aug. 14, 2024, 8:10 a.m. UTC 
This series (or equivalent) is a prerequisite for both user-mode pointer
masking and CFI support, as both of those are per-thread features and
are controlled by fields in the envcfg CSR. These patches are based on
v1 of the pointer masking series[1], with significant input from both
Deepak and Andrew.

[1]: https://lore.kernel.org/linux-riscv/20240319215915.832127-6-samuel.holland@sifive.com/

Changes in v4:
 - Rebase on riscv/for-next (v6.11-rc)
 - Add Conor's Reviewed-by tags from v2 (missed in v3)

Changes in v3:
 - Rebase on riscv/for-next
 - Drop use of __initdata due to conflicts with cpufeature.c refactoring

Changes in v2:
 - Rebase on riscv/for-next

Samuel Holland (3):
  riscv: Enable cbo.zero only when all harts support Zicboz
  riscv: Add support for per-thread envcfg CSR values
  riscv: Call riscv_user_isa_enable() only on the boot hart

 arch/riscv/include/asm/cpufeature.h |  2 +-
 arch/riscv/include/asm/processor.h  |  1 +
 arch/riscv/include/asm/switch_to.h  |  8 ++++++++
 arch/riscv/kernel/cpufeature.c      | 11 ++++++++---
 arch/riscv/kernel/smpboot.c         |  2 --
 arch/riscv/kernel/suspend.c         |  4 ++--
 6 files changed, 20 insertions(+), 8 deletions(-)

Comments

patchwork-bot+linux-riscv@kernel.org Oct. 6, 2024, 1:29 p.m. UTC | #1 
Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Wed, 14 Aug 2024 01:10:53 -0700 you wrote:
> This series (or equivalent) is a prerequisite for both user-mode pointer
> masking and CFI support, as both of those are per-thread features and
> are controlled by fields in the envcfg CSR. These patches are based on
> v1 of the pointer masking series[1], with significant input from both
> Deepak and Andrew.
> 
> [1]: https://lore.kernel.org/linux-riscv/20240319215915.832127-6-samuel.holland@sifive.com/
> 
> [...]

Here is the summary with links:
  - [v4,1/3] riscv: Enable cbo.zero only when all harts support Zicboz
    https://git.kernel.org/riscv/c/1b57747e978f
  - [v4,2/3] riscv: Add support for per-thread envcfg CSR values
    https://git.kernel.org/riscv/c/5fc7355f0137
  - [v4,3/3] riscv: Call riscv_user_isa_enable() only on the boot hart
    https://git.kernel.org/riscv/c/368546ebe7e7

You are awesome, thank you!