Show patches with: Archived = No       |   15084 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[V5,05/11] riscv: traps: Add noinstr to prevent instrumentation inserted riscv: Add GENERIC_ENTRY support and related features - - - --- 2022-09-18 Guo Ren Superseded
[V5,04/11] compiler_types.h: Add __noinstr_section() for noinstr riscv: Add GENERIC_ENTRY support and related features - 2 - --- 2022-09-18 Guo Ren Superseded
[V5,03/11] riscv: ptrace: Remove duplicate operation riscv: Add GENERIC_ENTRY support and related features - 1 - --- 2022-09-18 Guo Ren Superseded
[V5,02/11] riscv: compat_syscall_table: Fixup compile warning riscv: Add GENERIC_ENTRY support and related features - 1 - --- 2022-09-18 Guo Ren Superseded
[V5,01/11] riscv: elf_kexec: Fixup compile warning riscv: Add GENERIC_ENTRY support and related features - 1 - --- 2022-09-18 Guo Ren Superseded
[v5,10/10] riscv: dts: microchip: add a devicetree for aries' m100pfsevp New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-16 Conor Dooley Superseded
[v5,09/10] riscv: dts: microchip: add sevkit device tree New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-16 Conor Dooley Superseded
[v5,08/10] riscv: dts: microchip: reduce the fic3 clock rate New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-16 Conor Dooley Superseded
[v5,07/10] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-16 Conor Dooley Superseded
[v5,06/10] riscv: dts: microchip: icicle: update pci address properties New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-16 Conor Dooley Superseded
[v5,05/10] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-16 Conor Dooley Superseded
[v5,04/10] riscv: dts: microchip: add pci dma ranges for the icicle kit New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-16 Conor Dooley Superseded
[v5,03/10] dt-bindings: riscv: microchip: document the sev kit New PolarFire SoC devkit devicetrees & 22.09 reference design updates - 1 - --- 2022-09-16 Conor Dooley Superseded
[v5,02/10] dt-bindings: riscv: microchip: document the aries m100pfsevp New PolarFire SoC devkit devicetrees & 22.09 reference design updates 1 - - --- 2022-09-16 Conor Dooley Superseded
[v5,01/10] dt-bindings: riscv: microchip: document icicle reference design New PolarFire SoC devkit devicetrees & 22.09 reference design updates 1 - - --- 2022-09-16 Conor Dooley Superseded
[3/3] riscv: ftrace: Reduce the detour code size to half riscv: ftrace: Fixup ftrace detour code - - - --- 2022-09-16 Guo Ren Superseded
[2/3] riscv: ftrace: Remove wasted nops for !RISCV_ISA_C riscv: ftrace: Fixup ftrace detour code - - - --- 2022-09-16 Guo Ren Superseded
[1/3] riscv: ftrace: Fixup panic by disabling preemption riscv: ftrace: Fixup ftrace detour code - - - --- 2022-09-16 Guo Ren Superseded
riscv: ztso: disallow elf binaries needing TSO riscv: ztso: disallow elf binaries needing TSO - - - --- 2022-09-16 Vineet Gupta Superseded
[v4,2/2] riscv: Allow PROT_WRITE-only mmap() Make mmap() with PROT_WRITE imply PROT_READ - 1 - --- 2022-09-15 Andrew Bresticker palmer Accepted
[v4,1/2] riscv: Make VM_WRITE imply VM_READ Make mmap() with PROT_WRITE imply PROT_READ - 1 - --- 2022-09-15 Andrew Bresticker palmer Accepted
[v3,10/10] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Add support for Renesas RZ/Five SoC - 2 - --- 2022-09-15 Lad, Prabhakar Superseded
[v3,09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Add support for Renesas RZ/Five SoC - 1 - --- 2022-09-15 Lad, Prabhakar Superseded
[v3,08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Add support for Renesas RZ/Five SoC - - - --- 2022-09-15 Lad, Prabhakar Superseded
[v3,07/10] riscv: boot: dts: r9a07g043: Add placeholder nodes Add support for Renesas RZ/Five SoC - - - --- 2022-09-15 Lad, Prabhakar Superseded
[v3,06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Add support for Renesas RZ/Five SoC - 2 - --- 2022-09-15 Lad, Prabhakar Superseded
[v3,05/10] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Add support for Renesas RZ/Five SoC - 1 - --- 2022-09-15 Lad, Prabhakar Superseded
[v3,04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Add support for Renesas RZ/Five SoC 1 1 - --- 2022-09-15 Lad, Prabhakar Superseded
[v3,03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Add support for Renesas RZ/Five SoC 1 1 - --- 2022-09-15 Lad, Prabhakar Superseded
[v3,02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Add support for Renesas RZ/Five SoC - 3 - --- 2022-09-15 Lad, Prabhakar Superseded
[v3,01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Add support for Renesas RZ/Five SoC - 1 - --- 2022-09-15 Lad, Prabhakar Superseded
[v1] RISC-V: KVM: Allow Guest use Zihintpause extension [v1] RISC-V: KVM: Allow Guest use Zihintpause extension - - - --- 2022-09-15 Mayuresh Chitale Superseded
[v5,7/7] riscv: Add cache information in AUX vector Use composable cache instead of L2 cache - 1 - --- 2022-09-13 Zong Li palmer Accepted
[v5,6/7] soc: sifive: ccache: define the macro for the register shifts Use composable cache instead of L2 cache - 1 - --- 2022-09-13 Zong Li palmer Accepted
[v5,5/7] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Use composable cache instead of L2 cache - 1 - --- 2022-09-13 Zong Li palmer Accepted
[v5,4/7] soc: sifive: ccache: reduce printing on init Use composable cache instead of L2 cache - 1 - --- 2022-09-13 Zong Li palmer Accepted
[v5,3/7] soc: sifive: ccache: determine the cache level from dts Use composable cache instead of L2 cache - 1 - --- 2022-09-13 Zong Li palmer Accepted
[v5,2/7] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Use composable cache instead of L2 cache - 1 - --- 2022-09-13 Zong Li palmer Accepted
[v5,1/7] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Use composable cache instead of L2 cache - 2 - --- 2022-09-13 Zong Li palmer Accepted
[V2,3/3] arm64/kprobe: Optimize the performance of patching single-step slot kprobe: Optimize the performance of patching ss - - - --- 2022-09-13 Liao, Chang Superseded
[V2,2/3] csky/kprobe: Optimize the performance of patching single-step slot kprobe: Optimize the performance of patching ss - - - --- 2022-09-13 Liao, Chang Superseded
[V2,1/3] riscv/kprobe: Optimize the performance of patching single-step slot kprobe: Optimize the performance of patching ss - - - --- 2022-09-13 Liao, Chang Superseded
[v4,6/6] soc: sifive: ccache: define the macro for the register shifts Use composable cache instead of L2 cache - 1 - --- 2022-09-12 Zong Li Superseded
[v4,5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Use composable cache instead of L2 cache - 1 - --- 2022-09-12 Zong Li Superseded
[v4,4/6] soc: sifive: ccache: reduce printing on init Use composable cache instead of L2 cache - 1 - --- 2022-09-12 Zong Li Superseded
[v4,3/6] soc: sifive: ccache: determine the cache level from dts Use composable cache instead of L2 cache - 1 - --- 2022-09-12 Zong Li Superseded
[v4,2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Use composable cache instead of L2 cache - 1 - --- 2022-09-12 Zong Li Superseded
[v4,1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Use composable cache instead of L2 cache - 2 - --- 2022-09-12 Zong Li Superseded
[v2] riscv: vdso: fix NULL deference in vdso_join_timens() when vfork [v2] riscv: vdso: fix NULL deference in vdso_join_timens() when vfork - - 1 --- 2022-09-08 Jisheng Zhang Superseded
[v3,6/6] soc: sifive: ccache: define the macro for the register shifts Use composable cache instead of L2 cache - 1 - --- 2022-09-08 Zong Li Superseded
[v3,5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Use composable cache instead of L2 cache - 1 - --- 2022-09-08 Zong Li Superseded
[v3,4/6] soc: sifive: ccache: reduce printing on init Use composable cache instead of L2 cache - 1 - --- 2022-09-08 Zong Li Superseded
[v3,3/6] soc: sifive: ccache: determine the cache level from dts Use composable cache instead of L2 cache - 1 - --- 2022-09-08 Zong Li Superseded
[v3,2/6] soc: sifive: ccache: rename SiFive L2 cache to Composable cache. Use composable cache instead of L2 cache - 1 - --- 2022-09-08 Zong Li Superseded
[v3,1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Use composable cache instead of L2 cache - 1 - --- 2022-09-08 Zong Li Superseded
[v4,10/10] riscv: dts: microchip: add a devicetree for aries' m100pfsevp New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-08 Conor Dooley Superseded
[v4,09/10] riscv: dts: microchip: add sevkit device tree New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-08 Conor Dooley Superseded
[v4,08/10] riscv: dts: microchip: reduce the fic3 clock rate New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-08 Conor Dooley Superseded
[v4,07/10] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-08 Conor Dooley Superseded
[v4,06/10] riscv: dts: microchip: icicle: update pci address properties New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-08 Conor Dooley Superseded
[v4,05/10] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-08 Conor Dooley Superseded
[v4,04/10] riscv: dts: microchip: add pci dma ranges for the icicle kit New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-08 Conor Dooley Superseded
[v4,03/10] dt-bindings: riscv: microchip: document the sev kit New PolarFire SoC devkit devicetrees & 22.09 reference design updates - 1 - --- 2022-09-08 Conor Dooley Superseded
[v4,02/10] dt-bindings: riscv: microchip: document the aries m100pfsevp New PolarFire SoC devkit devicetrees & 22.09 reference design updates 1 - - --- 2022-09-08 Conor Dooley Superseded
[v4,01/10] dt-bindings: riscv: microchip: document icicle reference design New PolarFire SoC devkit devicetrees & 22.09 reference design updates 1 - - --- 2022-09-08 Conor Dooley Superseded
[v2,2/2] RISC-V: KVM: Expose Zicbom to the guest riscv: KVM: Expose Zicbom to the guest - - - --- 2022-09-06 Andrew Jones Superseded
[v2,1/2] RISC-V: KVM: Provide UAPI for Zicbom block size riscv: KVM: Expose Zicbom to the guest - - - --- 2022-09-06 Andrew Jones Superseded
[3/3] RISC-V: KVM: Expose Zicbom to the guest riscv: KVM: Expose Zicbom to the guest - - - --- 2022-09-06 Andrew Jones Superseded
[2/3] RISC-V: KVM: Provide UAPI for Zicbom block size riscv: KVM: Expose Zicbom to the guest - - - --- 2022-09-06 Andrew Jones Superseded
[1/3] RISC-V: Output cbom-block-size riscv: KVM: Expose Zicbom to the guest - - - --- 2022-09-06 Andrew Jones Superseded
[V3,7/7] riscv: Add config of thread stack size riscv: Add GENERIC_ENTRY, irq stack support - - - --- 2022-09-06 Guo Ren Superseded
[V3,6/7] riscv: Support HAVE_SOFTIRQ_ON_OWN_STACK riscv: Add GENERIC_ENTRY, irq stack support - - - --- 2022-09-06 Guo Ren Superseded
[V3,5/7] riscv: Support HAVE_IRQ_EXIT_ON_IRQ_STACK riscv: Add GENERIC_ENTRY, irq stack support - - - --- 2022-09-06 Guo Ren Superseded
[V3,4/7] riscv: convert to generic entry riscv: Add GENERIC_ENTRY, irq stack support - - - --- 2022-09-06 Guo Ren Superseded
[V3,3/7] riscv: ptrace: Remove duplicate operation riscv: Add GENERIC_ENTRY, irq stack support - 1 - --- 2022-09-06 Guo Ren Superseded
[V3,2/7] riscv: compat_syscall_table: Fixup compile warning riscv: Add GENERIC_ENTRY, irq stack support - 1 - --- 2022-09-06 Guo Ren Superseded
[V3,1/7] riscv: elf_kexec: Fixup compile warning riscv: Add GENERIC_ENTRY, irq stack support - 1 - --- 2022-09-06 Guo Ren Superseded
[v2,5/5] riscv: check for kernel config option in t-head memory types errata Some style cleanups for recent extension additions - 3 - --- 2022-09-05 Heiko Stübner palmer Accepted
[v2,4/5] riscv: use BIT() marco for cpufeature probing Some style cleanups for recent extension additions - 2 - --- 2022-09-05 Heiko Stübner palmer Accepted
[v2,3/5] riscv: use BIT() macros in t-head errata init Some style cleanups for recent extension additions - 3 - --- 2022-09-05 Heiko Stübner palmer Accepted
[v2,2/5] riscv: drop some idefs from CMO initialization Some style cleanups for recent extension additions - 3 - --- 2022-09-05 Heiko Stübner palmer Accepted
[v2,1/5] riscv: cleanup svpbmt cpufeature probing Some style cleanups for recent extension additions - 3 - --- 2022-09-05 Heiko Stübner palmer Accepted
[v2,6/6] EDAC/sifive: use sifive_ccache instead of sifive_l2 Use composable cache instead of L2 cache - - - --- 2022-09-05 Zong Li Superseded
[v2,5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Use composable cache instead of L2 cache - 1 - --- 2022-09-05 Zong Li Superseded
[v2,4/6] soc: sifive: ccache: reduce printing on init Use composable cache instead of L2 cache - - - --- 2022-09-05 Zong Li Superseded
[v2,3/6] soc: sifive: ccache: determine the cache level from dts Use composable cache instead of L2 cache - - - --- 2022-09-05 Zong Li Superseded
[v2,2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Use composable cache instead of L2 cache - - - --- 2022-09-05 Zong Li Superseded
[v2,1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Use composable cache instead of L2 cache - 2 - --- 2022-09-05 Zong Li Superseded
[v2] riscv: lib: optimize memcmp with ld insn [v2] riscv: lib: optimize memcmp with ld insn - 1 - --- 2022-09-02 Yipeng Zou Superseded
[v3] riscv: Fix permissions for all mm's during mm init [v3] riscv: Fix permissions for all mm's during mm init - 2 - --- 2022-09-02 Vladimir Isaev Superseded
[v2,3/3] riscv: dts: starfive: Add StarFive VisionFive V1 device tree Enable initial support for StarFive VisionFive V1 SBC - 1 - --- 2022-09-02 Cristian Ciocaltea Superseded
[v2,2/3] riscv: dts: starfive: Add common DT for JH7100 based boards Enable initial support for StarFive VisionFive V1 SBC - 1 - --- 2022-09-02 Cristian Ciocaltea Superseded
[v2,1/3] dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board Enable initial support for StarFive VisionFive V1 SBC - 2 - --- 2022-09-02 Cristian Ciocaltea Superseded
RISC-V: Add support for Ztso RISC-V: Add support for Ztso - - - --- 2022-09-02 Palmer Dabbelt Changes Requested
[3/3] riscv: dts: starfive: Add StarFive VisionFive V1 device tree Enable initial support for StarFive VisionFive V1 SBC - - - --- 2022-09-01 Cristian Ciocaltea Superseded
[2/3] riscv: dts: starfive: Add common DT for JH7100 based boards Enable initial support for StarFive VisionFive V1 SBC - - - --- 2022-09-01 Cristian Ciocaltea Superseded
[1/3] dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board Enable initial support for StarFive VisionFive V1 SBC - - - --- 2022-09-01 Cristian Ciocaltea Superseded
[v3,9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-01 Conor Dooley Superseded
[v3,8/9] riscv: dts: microchip: add sevkit device tree New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-01 Conor Dooley Superseded
[v3,7/9] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses New PolarFire SoC devkit devicetrees & 22.09 reference design updates - - - --- 2022-09-01 Conor Dooley Superseded
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