Show patches with: Series = Add Counter delegation ISA extension support       |    State = Action Required       |    Archived = No       |   21 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,21/21] Sync empty-pmu-events.c with autogenerated one Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,20/21] tools/perf: Pass the Counter constraint values in the pmu events Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,19/21] tools/perf: Support event code for arch standard events Add Counter delegation ISA extension support - - - --- 2025-01-14 Atish Patra New
[v2,18/21] RISC-V: perf: Add Qemu virt machine events Add Counter delegation ISA extension support - - - --- 2025-01-14 Atish Patra New
[v2,17/21] RISC-V: perf: Add legacy event encodings via sysfs Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Add Counter delegation ISA extension support - - - --- 2025-01-14 Atish Patra New
[v2,15/21] RISC-V: perf: Skip PMU SBI extension when not implemented Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,14/21] RISC-V: perf: Implement supervisor counter delegation support Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,13/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Add Counter delegation ISA extension support - - - --- 2025-01-14 Atish Patra New
[v2,12/21] RISC-V: perf: Modify the counter discovery mechanism Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,11/21] RISC-V: perf: Restructure the SBI PMU code Add Counter delegation ISA extension support - - - --- 2025-01-14 Atish Patra New
[v2,10/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,09/21] RISC-V: Add Smcntrpmf extension parsing Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,08/21] dt-bindings: riscv: add Ssccfg ISA extension description Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,07/21] RISC-V: Add Ssccfg ISA extension definition and parsing Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,06/21] RISC-V: Add Sscfg extension CSR definition Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,05/21] RISC-V: Define indirect CSR access helpers Add Counter delegation ISA extension support - - - --- 2025-01-14 Atish Patra New
[v2,04/21] dt-bindings: riscv: add Sxcsrind ISA extension description Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,03/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New
[v2,01/21] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware… Add Counter delegation ISA extension support - - - --1 2025-01-14 Atish Patra New