Show patches with: Submitter = Jesse Taube       |    State = Action Required       |    Archived = No       |   10 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2] RISC-V: hwprobe: Use BIT macro to avoid warnings [v2] RISC-V: hwprobe: Use BIT macro to avoid warnings - 1 1 13-- 2024-08-22 Jesse Taube New
[v9,6/6] RISC-V: hwprobe: Document unaligned vector perf key RISC-V: Detect and report speed of unaligned vector accesses - 1 - 13-- 2024-08-20 Jesse Taube New
[v9,5/6] RISC-V: Report vector unaligned access speed hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 1 - 121- 2024-08-20 Jesse Taube New
[v9,4/6] RISC-V: Detect unaligned vector accesses supported RISC-V: Detect and report speed of unaligned vector accesses - 1 - 121- 2024-08-20 Jesse Taube New
[v9,3/6] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED RISC-V: Detect and report speed of unaligned vector accesses - 3 - 13-- 2024-08-20 Jesse Taube New
[v9,2/6] RISC-V: Scalar unaligned access emulated on hotplug CPUs RISC-V: Detect and report speed of unaligned vector accesses - 1 - 13-- 2024-08-20 Jesse Taube New
[v9,1/6] RISC-V: Check scalar unaligned access on all CPUs RISC-V: Detect and report speed of unaligned vector accesses - 2 - 13-- 2024-08-20 Jesse Taube New
[2/2] dt-bindings: riscv: Add Zicclsm ISA extension description. RISC-V: Add Zicclsm extension support 1 1 - 13-- 2024-08-09 Jesse Taube New
[1/2] RISC-V: Add Zicclsm to cpufeature and hwprobe RISC-V: Add Zicclsm extension support - 3 1 121- 2024-08-09 Jesse Taube New
[1/1] RISC-V: Add parameter to unaligned access speed [1/1] RISC-V: Add parameter to unaligned access speed - - - --1 2024-08-05 Jesse Taube New