Show patches with: Submitter = Xu Lu       |    State = Action Required       |    Archived = No       |   11 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
iommu: riscv: Split 8-byte accesses on 32 bit I/O bus platform iommu: riscv: Split 8-byte accesses on 32 bit I/O bus platform - - - 121- 2025-03-25 Xu Lu New
[RESEND,v2,4/4] iommu/riscv: Add support for Svnapot riscv: iommu: Support Svnapot - - - 13-- 2025-03-18 Xu Lu New
[RESEND,v2,3/4] iommu/riscv: Introduce IOMMU page table lock riscv: iommu: Support Svnapot - - - 13-- 2025-03-18 Xu Lu New
[RESEND,v2,2/4] iommu/riscv: Use pte_t to represent page table entry riscv: iommu: Support Svnapot - - - 13-- 2025-03-18 Xu Lu New
[RESEND,v2,1/4] mm/gup: Add huge pte handling logic in follow_page_pte() riscv: iommu: Support Svnapot - - - 13-- 2025-03-18 Xu Lu New
[5/5] irqchip/aclint-sswi: Use wmb() to order normal writes and IPI writes riscv: irqchip: Optimization of interrupt handling - - - 13-- 2025-01-13 Xu Lu New
[4/5] irqchip/timer-clint: Use wmb() to order normal writes and IPI writes riscv: irqchip: Optimization of interrupt handling - - - 13-- 2025-01-13 Xu Lu New
[3/5] irqchip/riscv-imsic: Use wmb() to order normal writes and IPI writes riscv: irqchip: Optimization of interrupt handling - - - 13-- 2025-01-13 Xu Lu New
[2/5] irqchip/riscv-imsic: Add a threshold to ext irq handling times riscv: irqchip: Optimization of interrupt handling - - - 121- 2025-01-13 Xu Lu New
[1/5] irqchip/riscv-intc: Balance priority and fairness during irq handling riscv: irqchip: Optimization of interrupt handling - - - 13-- 2025-01-13 Xu Lu New
[v2] riscv: mm: Fix alignment of phys_ram_base [v2] riscv: mm: Fix alignment of phys_ram_base - - - 121- 2024-12-03 Xu Lu New