| Message ID | 20181201000156.5366-1-andrea.parri@amarulasolutions.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv, atomic: Add #define's for the atomic_{cmp, }xchg_*() variants | expand |
On Sat, Dec 01, 2018 at 01:01:56AM +0100, Andrea Parri wrote: > If an architecture does not define the atomic_{cmp,}xchg_*() variants, > the generic implementation defaults them to the fully-ordered version. > > riscv's had its own variants since "the beginning", but it never told > (#define-d these for) the generic implementation: it is time to do so. > > Signed-off-by: Andrea Parri <andrea.parri@amarulasolutions.com> > Cc: Palmer Dabbelt <palmer@sifive.com> > Cc: Albert Ou <aou@eecs.berkeley.edu> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Peter Zijlstra <peterz@infradead.org> > Cc: Boqun Feng <boqun.feng@gmail.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> > --- > arch/riscv/include/asm/atomic.h | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h > index c452359c9cb8a..93826771b616a 100644 > --- a/arch/riscv/include/asm/atomic.h > +++ b/arch/riscv/include/asm/atomic.h > @@ -303,6 +303,15 @@ c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ > > ATOMIC_OPS() > > +#define atomic_xchg_relaxed atomic_xchg_relaxed > +#define atomic_xchg_acquire atomic_xchg_acquire > +#define atomic_xchg_release atomic_xchg_release > +#define atomic_xchg atomic_xchg > +#define atomic_cmpxchg_relaxed atomic_cmpxchg_relaxed > +#define atomic_cmpxchg_acquire atomic_cmpxchg_acquire > +#define atomic_cmpxchg_release atomic_cmpxchg_release > +#define atomic_cmpxchg atomic_cmpxchg > + > #undef ATOMIC_OPS > #undef ATOMIC_OP > > -- > 2.17.1 >
diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index c452359c9cb8a..93826771b616a 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -303,6 +303,15 @@ c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ ATOMIC_OPS() +#define atomic_xchg_relaxed atomic_xchg_relaxed +#define atomic_xchg_acquire atomic_xchg_acquire +#define atomic_xchg_release atomic_xchg_release +#define atomic_xchg atomic_xchg +#define atomic_cmpxchg_relaxed atomic_cmpxchg_relaxed +#define atomic_cmpxchg_acquire atomic_cmpxchg_acquire +#define atomic_cmpxchg_release atomic_cmpxchg_release +#define atomic_cmpxchg atomic_cmpxchg + #undef ATOMIC_OPS #undef ATOMIC_OP
If an architecture does not define the atomic_{cmp,}xchg_*() variants, the generic implementation defaults them to the fully-ordered version. riscv's had its own variants since "the beginning", but it never told (#define-d these for) the generic implementation: it is time to do so. Signed-off-by: Andrea Parri <andrea.parri@amarulasolutions.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Will Deacon <will.deacon@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Boqun Feng <boqun.feng@gmail.com> --- TBH, the delay was not intentional: I've just become aware of it while working on moving riscv over to queued rwlocks. There's currently one callsite for the non-fully-ordered variants mentioned above for riscv: for atomic_cmpxchg_acquire() in kernel/sched/rt.c:rto_start_trylock(), [before] 51a: 100726af lr.w a3,(a4) 51e: 00069763 bnez a3,52c <.L17> 522: 1af7262f sc.w.rl a2,a5,(a4) 526: fa75 bnez a2,51a <.L1> 528: 0330000f fence rw,rw [after] 51a: 100726af lr.w a3,(a4) 51e: 00069763 bnez a3,52c <.L17> 522: 18f7262f sc.w a2,a5,(a4) 526: fa75 bnez a2,51a <.L1> 528: 0230000f fence r,rw --- arch/riscv/include/asm/atomic.h | 9 +++++++++ 1 file changed, 9 insertions(+)