diff mbox series

[v4,1/4] riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED

Message ID 20210604114950.1446390-2-alex@ghiti.fr (mailing list archive)
State New
Headers show
Series riscv: Map the kernel with correct permissions the first time | expand

Commit Message

Alex Ghiti June 4, 2021, 11:49 a.m. UTC
Make the physical RAM base address available for all kernels, not only
XIP kernels as it will allow to simplify address conversions macros.

Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
---
 arch/riscv/Kconfig | 6 ------
 1 file changed, 6 deletions(-)

Comments

Emil Renner Berthing June 12, 2021, 11:23 p.m. UTC | #1
On Fri, 4 Jun 2021 at 13:51, Alexandre Ghiti <alex@ghiti.fr> wrote:
>
> Make the physical RAM base address available for all kernels, not only
> XIP kernels as it will allow to simplify address conversions macros.

Am I just reading it wrong or won't this patch make it so that the same kernel
can't run on two chips with physical ram starting at different addresses?

/Emil

> ---
>  arch/riscv/Kconfig | 6 ------
>  1 file changed, 6 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index b58596b141fc..3d8e7e4bb45c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -493,13 +493,8 @@ config STACKPROTECTOR_PER_TASK
>         def_bool y
>         depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS
>
> -config PHYS_RAM_BASE_FIXED
> -       bool "Explicitly specified physical RAM address"
> -       default n
> -
>  config PHYS_RAM_BASE
>         hex "Platform Physical RAM address"
> -       depends on PHYS_RAM_BASE_FIXED
>         default "0x80000000"
>         help
>           This is the physical address of RAM in the system. It has to be
> @@ -512,7 +507,6 @@ config XIP_KERNEL
>         # This prevents XIP from being enabled by all{yes,mod}config, which
>         # fail to build since XIP doesn't support large kernels.
>         depends on !COMPILE_TEST
> -       select PHYS_RAM_BASE_FIXED
>         help
>           Execute-In-Place allows the kernel to run from non-volatile storage
>           directly addressable by the CPU, such as NOR flash. This saves RAM
> --
> 2.30.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Palmer Dabbelt June 13, 2021, 12:23 a.m. UTC | #2
On Sat, 12 Jun 2021 16:23:03 PDT (-0700), emil.renner.berthing@gmail.com wrote:
> On Fri, 4 Jun 2021 at 13:51, Alexandre Ghiti <alex@ghiti.fr> wrote:
>>
>> Make the physical RAM base address available for all kernels, not only
>> XIP kernels as it will allow to simplify address conversions macros.
>
> Am I just reading it wrong or won't this patch make it so that the same kernel
> can't run on two chips with physical ram starting at different addresses?

IIUC we were in that position, at least without relocatable kernels.  
Maybe I'm misunderstanding this, though?

>
> /Emil
>
>> ---
>>  arch/riscv/Kconfig | 6 ------
>>  1 file changed, 6 deletions(-)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index b58596b141fc..3d8e7e4bb45c 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -493,13 +493,8 @@ config STACKPROTECTOR_PER_TASK
>>         def_bool y
>>         depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS
>>
>> -config PHYS_RAM_BASE_FIXED
>> -       bool "Explicitly specified physical RAM address"
>> -       default n
>> -
>>  config PHYS_RAM_BASE
>>         hex "Platform Physical RAM address"
>> -       depends on PHYS_RAM_BASE_FIXED
>>         default "0x80000000"
>>         help
>>           This is the physical address of RAM in the system. It has to be
>> @@ -512,7 +507,6 @@ config XIP_KERNEL
>>         # This prevents XIP from being enabled by all{yes,mod}config, which
>>         # fail to build since XIP doesn't support large kernels.
>>         depends on !COMPILE_TEST
>> -       select PHYS_RAM_BASE_FIXED
>>         help
>>           Execute-In-Place allows the kernel to run from non-volatile storage
>>           directly addressable by the CPU, such as NOR flash. This saves RAM
>> --
>> 2.30.2
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
diff mbox series

Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b58596b141fc..3d8e7e4bb45c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -493,13 +493,8 @@  config STACKPROTECTOR_PER_TASK
 	def_bool y
 	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS
 
-config PHYS_RAM_BASE_FIXED
-	bool "Explicitly specified physical RAM address"
-	default n
-
 config PHYS_RAM_BASE
 	hex "Platform Physical RAM address"
-	depends on PHYS_RAM_BASE_FIXED
 	default "0x80000000"
 	help
 	  This is the physical address of RAM in the system. It has to be
@@ -512,7 +507,6 @@  config XIP_KERNEL
 	# This prevents XIP from being enabled by all{yes,mod}config, which
 	# fail to build since XIP doesn't support large kernels.
 	depends on !COMPILE_TEST
-	select PHYS_RAM_BASE_FIXED
 	help
 	  Execute-In-Place allows the kernel to run from non-volatile storage
 	  directly addressable by the CPU, such as NOR flash. This saves RAM