| Message ID | 20220815050815.22340-3-samuel@sholland.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Allwinner D1 platform support | expand |
Am Montag, 15. August 2022, 07:08:05 CEST schrieb Samuel Holland: > The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. > Notably, the C906 core is used in the Allwinner D1 SoC. > > Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
On Mon, 15 Aug 2022 00:08:05 -0500, Samuel Holland wrote: > The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. > Notably, the C906 core is used in the Allwinner D1 SoC. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
在 2022-08-15星期一的 00:08 -0500，Samuel Holland写道： > The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. > Notably, the C906 core is used in the Allwinner D1 SoC. Could this get applied first? C906 and C910 now have a fixed-configuration open-source version, which means these cores could be played by anyone, and having them in the DT binding really helps people. In addition I am aware of some C906- equipped SoC out of Allwinner. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml > b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 873dd12f6e89..ce2161d9115a 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -38,6 +38,8 @@ properties: > - sifive,u5 > - sifive,u7 > - canaan,k210 > + - thead,c906 > + - thead,c910 > - const: riscv > - items: > - enum:
On Fri, Nov 04, 2022 at 10:57:58AM +0800, Icenowy Zheng wrote: > 在 2022-08-15星期一的 00:08 -0500，Samuel Holland写道： > > The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. > > Notably, the C906 core is used in the Allwinner D1 SoC. > > Could this get applied first? > > C906 and C910 now have a fixed-configuration open-source version, which > means these cores could be played by anyone, and having them in the DT > binding really helps people. In addition I am aware of some C906- > equipped SoC out of Allwinner. I've applied this one patch as v6.2 material since I doubt this series is gonna make it & the Bouffalolabs dt is going to need this compatible too. I applied it on top of v6.1-rc1 just in case: https://git.kernel.org/conor/c/0d814000ad3589bf4f69c9cb25a3b77bbd55ffec > > > > > Signed-off-by: Samuel Holland <samuel@sholland.org> > > --- > > > > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml > > b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index 873dd12f6e89..ce2161d9115a 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -38,6 +38,8 @@ properties: > > - sifive,u5 > > - sifive,u7 > > - canaan,k210 > > + - thead,c906 > > + - thead,c910 > > - const: riscv > > - items: > > - enum: >
On Sun, Nov 20, 2022 at 11:23:42AM +0000, Conor Dooley wrote: > On Fri, Nov 04, 2022 at 10:57:58AM +0800, Icenowy Zheng wrote: > > 在 2022-08-15星期一的 00:08 -0500，Samuel Holland写道： > > > The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. > > > Notably, the C906 core is used in the Allwinner D1 SoC. > > > > Could this get applied first? > > > > C906 and C910 now have a fixed-configuration open-source version, which > > means these cores could be played by anyone, and having them in the DT > > binding really helps people. In addition I am aware of some C906- > > equipped SoC out of Allwinner. > > I've applied this one patch as v6.2 material since I doubt this series is > gonna make it & the Bouffalolabs dt is going to need this compatible too. > I applied it on top of v6.1-rc1 just in case: > > https://git.kernel.org/conor/c/0d814000ad3589bf4f69c9cb25a3b77bbd55ffec Woops, totally the wrong hash. Fixed: https://git.kernel.org/conor/c/41adc2fbad8bc42ed5fdf480e5318133a4941bbb Thanks, Conor.
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 873dd12f6e89..ce2161d9115a 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -38,6 +38,8 @@ properties: - sifive,u5 - sifive,u7 - canaan,k210 + - thead,c906 + - thead,c910 - const: riscv - items: - enum:
The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C906 core is used in the Allwinner D1 SoC. Signed-off-by: Samuel Holland <samuel@sholland.org> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+)