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[RFC,13/27] clk: sifive: convert SOC_SIFIVE to ARCH_SIFIVE

Message ID	20220923185605.1900083-14-conor@kernel.org (mailing list archive)
State	RFC, archived
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Conor Dooley <conor@kernel.org> To: linux-riscv@lists.infradead.org Cc: palmer@dabbelt.com, damien.lemoal@opensource.wdc.com, geert@linux-mk68.org, heiko@sntech.de, kernel@esmil.dk, arnd@arndb.de, Conor Dooley <conor.dooley@microchip.com> Subject: [RFC 13/27] clk: sifive: convert SOC_SIFIVE to ARCH_SIFIVE Date: Fri, 23 Sep 2022 19:55:52 +0100 Message-Id: <20220923185605.1900083-14-conor@kernel.org> In-Reply-To: <20220923185605.1900083-1-conor@kernel.org> References: <20220923185605.1900083-1-conor@kernel.org> MIME-Version: 1.0 Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	RISC-V: Convert SOC_FOO symbols to ARCH_FOO \| expand [RFC,00/27] RISC-V: Convert SOC_FOO symbols to ARCH_FOO [RFC,01/27] clk: microchip: replace SOC_MICROCHIP_POLARFIRE with ARCH_MICROCHIP [RFC,02/27] i2c: microchip-corei2c: replace SOC_MICROCHIP_POLARFIRE with ARCH_MICROCHIP [RFC,03/27] mailbox: mpfs: replace SOC_MICROCHIP_POLARFIRE with ARCH_MICROCHIP [RFC,04/27] usb: musb: mpfs: replace SOC_MICROCHIP_POLARFIRE with ARCH_MICROCHIP [RFC,05/27] rtc: mpfs: replace SOC_MICROCHIP_POLARFIRE with ARCH_MICROCHIP [RFC,06/27] riscv: stop selecting the PolarFire SoC clock driver [RFC,07/27] riscv: replace SOC_STARFIVE with ARCH_STARFIVE [RFC,08/27] clk: starfive: replace SOC_STARFIVE with ARCH_STARFIVE [RFC,09/27] pinctrl: starfive: replace SOC_STARFIVE with ARCH_STARFIVE [RFC,10/27] reset: starfive: replace SOC_STARFIVE with ARCH_STARFIVE [RFC,11/27] riscv: replace SOC_SIFIVE with ARCH_SIFIVE [RFC,12/27] soc: sifive: convert SOC_SIFIVE to ARCH_SIFIVE [RFC,13/27] clk: sifive: convert SOC_SIFIVE to ARCH_SIFIVE [RFC,14/27] clk: sifive: select by default if ARCH_SIFIVE [RFC,15/27] serial: sifive: select by default if ARCH_SIFIVE [RFC,16/27] PCI: dwc: fu740: convert SOC_SIFIVE to ARCH_SIFIVE [RFC,17/27] riscv: stop selecting SiFive clock and serial drivers directly [RFC,18/27] riscv: convert SOC_VIRT to ARCH_VIRT [RFC,19/27] kunit: tool: rename SOC_VIRT to ARCH_VIRT in riscv's QEMU config [RFC,20/27] wireguard: selftests: swap SOC_VIRT for ARCH_VIRT on riscv [RFC,21/27] riscv: convert SOC_CANAAN to ARCH_CANAAN [RFC,22/27] clk: k210: convert SOC_CANAAN to ARCH_CANAAN [RFC,23/27] pinctrl: k210: convert SOC_CANAAN to ARCH_CANAAN [RFC,24/27] soc: k210: convert SOC_CANAAN to ARCH_CANAAN [RFC,25/27] reset: k210: convert SOC_CANAAN to ARCH_CANAAN [RFC,26/27] serial: sifive: select by default if ARCH_CANAAN [RFC,27/27] riscv: stop directly selecting drivers for ARCH_CANAAN

Commit Message

Conor Dooley Sept. 23, 2022, 6:55 p.m. UTC

From: Conor Dooley <conor.dooley@microchip.com>

At LPC we decided to convert all of the SOC_ symbols in arch/riscv to
ARCH_ for consistency between "incumbent" vendors and those with a
legacy from other architectures. To that end, swap SOC_SIFIVE for
ARCH_SIFIVE & depend on it rather than RISCV.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/clk/sifive/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index 9132c3c4aa86..b21f4cbc3583 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -2,7 +2,7 @@ 
 
 menuconfig CLK_SIFIVE
 	bool "SiFive SoC driver support"
-	depends on RISCV || COMPILE_TEST
+	depends on ARCH_SIFIVE || COMPILE_TEST
 	help
 	  SoC drivers for SiFive Linux-capable SoCs.