| Message ID | 20221128102632.435174-10-heiko@sntech.de (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | Zbb string optimizations and call support in alternatives | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Guessing tree name failed |
On Mon, Nov 28, 2022 at 11:26:28AM +0100, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@vrull.eu> > RISC-V: add rd reg parsing to parse_asm header Same as all these patches, they need the header name fixed up :) > > Add a macro to allow parsing of the rd register from an instruction. > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Again, looks to be otherwise the same as what I left an R-b for on v1? Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/include/asm/insn.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h > index 1caed8fe5204..ef4b1c18cbdc 100644 > --- a/arch/riscv/include/asm/insn.h > +++ b/arch/riscv/include/asm/insn.h > @@ -60,6 +60,7 @@ > #define RVG_RS1_OPOFF 15 > #define RVG_RS2_OPOFF 20 > #define RVG_RD_OPOFF 7 > +#define RVG_RD_MASK GENMASK(4, 0) > > /* The bit field of immediate value in RVC J instruction */ > #define RVC_J_IMM_SIGN_OPOFF 12 > @@ -244,6 +245,10 @@ static __always_inline bool riscv_insn_is_branch(u32 code) > #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) > #define RVC_X(X, s, mask) RV_X(X, s, mask) > > +#define RV_EXTRACT_RD_REG(x) \ > + ({typeof(x) x_ = (x); \ > + (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); }) > + > #define RV_EXTRACT_UTYPE_IMM(x) \ > ({typeof(x) x_ = (x); \ > (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); }) > -- > 2.35.1 >
On Mon, Nov 28, 2022 at 11:26:28AM +0100, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@vrull.eu> > > Add a macro to allow parsing of the rd register from an instruction. > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > --- > arch/riscv/include/asm/insn.h | 5 +++++ > 1 file changed, 5 insertions(+) With Conor's $SUBJECT correction, Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index 1caed8fe5204..ef4b1c18cbdc 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -60,6 +60,7 @@ #define RVG_RS1_OPOFF 15 #define RVG_RS2_OPOFF 20 #define RVG_RD_OPOFF 7 +#define RVG_RD_MASK GENMASK(4, 0) /* The bit field of immediate value in RVC J instruction */ #define RVC_J_IMM_SIGN_OPOFF 12 @@ -244,6 +245,10 @@ static __always_inline bool riscv_insn_is_branch(u32 code) #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) #define RVC_X(X, s, mask) RV_X(X, s, mask) +#define RV_EXTRACT_RD_REG(x) \ + ({typeof(x) x_ = (x); \ + (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); }) + #define RV_EXTRACT_UTYPE_IMM(x) \ ({typeof(x) x_ = (x); \ (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })