| Message ID | 20230125142056.18356-5-andy.chiu@sifive.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | riscv: Add vector ISA support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 13 and now 13 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/alphanumeric_selects | success | Out of order selects before the patch: 57 and now 57 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 2 this patch: 2 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 29 lines checked |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Wed, Jan 25, 2023 at 02:20:41PM +0000, Andy Chiu wrote: > clear vector registers on boot if kernel supports V. > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> > [vineetg: broke this out to a seperate patch] > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> But this patch didn't carry over the long list of contributors from it's source? Seems a bit odd, that's all. There was also an Rb from Palmer that got dropped too. Was that intentional? https://lore.kernel.org/linux-riscv/20220921214439.1491510-6-stillson@rivosinc.com/ Thanks, Conor. > --- > arch/riscv/kernel/head.S | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S > index b865046e4dbb..ea803c96eeff 100644 > --- a/arch/riscv/kernel/head.S > +++ b/arch/riscv/kernel/head.S > @@ -431,6 +431,29 @@ ENTRY(reset_regs) > csrw fcsr, 0 > /* note that the caller must clear SR_FS */ > #endif /* CONFIG_FPU */ > + > +#ifdef CONFIG_RISCV_ISA_V > + csrr t0, CSR_MISA > + li t1, COMPAT_HWCAP_ISA_V > + and t0, t0, t1 > + beqz t0, .Lreset_regs_done > + > + /* > + * Clear vector registers and reset vcsr > + * VLMAX has a defined value, VLEN is a constant, > + * and this form of vsetvli is defined to set vl to VLMAX. > + */ > + li t1, SR_VS > + csrs CSR_STATUS, t1 > + csrs CSR_VCSR, x0 > + vsetvli t1, x0, e8, m8, ta, ma > + vmv.v.i v0, 0 > + vmv.v.i v8, 0 > + vmv.v.i v16, 0 > + vmv.v.i v24, 0 > + /* note that the caller must clear SR_VS */ > +#endif /* CONFIG_RISCV_ISA_V */ > + > .Lreset_regs_done: > ret > END(reset_regs) > -- > 2.17.1 >
On 1/25/23 13:54, Conor Dooley wrote: > n Wed, Jan 25, 2023 at 02:20:41PM +0000, Andy Chiu wrote: >> clear vector registers on boot if kernel supports V. >> >> Signed-off-by: Greentime Hu<greentime.hu@sifive.com> >> Signed-off-by: Vineet Gupta<vineetg@rivosinc.com> >> [vineetg: broke this out to a seperate patch] >> Signed-off-by: Andy Chiu<andy.chiu@sifive.com> > But this patch didn't carry over the long list of contributors from it's > source? Seems a bit odd, that's all. > There was also an Rb from Palmer that got dropped too. Was that > intentional? > https://lore.kernel.org/linux-riscv/20220921214439.1491510-6-stillson@rivosinc.com/ In v12 this and 5/19 were in one patch, which I broke off into two for clarity. Hence the Rb technically doesn't apply. -Vineet
On Wed, Jan 25, 2023 at 01:57:28PM -0800, Vineet Gupta wrote: > > On 1/25/23 13:54, Conor Dooley wrote: > > n Wed, Jan 25, 2023 at 02:20:41PM +0000, Andy Chiu wrote: > > > clear vector registers on boot if kernel supports V. > > > > > > Signed-off-by: Greentime Hu<greentime.hu@sifive.com> > > > Signed-off-by: Vineet Gupta<vineetg@rivosinc.com> > > > [vineetg: broke this out to a seperate patch] > > > Signed-off-by: Andy Chiu<andy.chiu@sifive.com> > > But this patch didn't carry over the long list of contributors from it's > > source? Seems a bit odd, that's all. > > There was also an Rb from Palmer that got dropped too. Was that > > intentional? > > https://lore.kernel.org/linux-riscv/20220921214439.1491510-6-stillson@rivosinc.com/ > > In v12 this and 5/19 were in one patch, which I broke off into two for > clarity. Hence the Rb technically doesn't apply. Technically correct, the best kind, huh? Anyways, I just noticed that this patch had a comment from Heiko that wasn't addressed to maybe the omission is for the better! https://lore.kernel.org/linux-riscv/2331455.NG923GbCHz@diego/ Thanks, Conor.
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index b865046e4dbb..ea803c96eeff 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -431,6 +431,29 @@ ENTRY(reset_regs) csrw fcsr, 0 /* note that the caller must clear SR_FS */ #endif /* CONFIG_FPU */ + +#ifdef CONFIG_RISCV_ISA_V + csrr t0, CSR_MISA + li t1, COMPAT_HWCAP_ISA_V + and t0, t0, t1 + beqz t0, .Lreset_regs_done + + /* + * Clear vector registers and reset vcsr + * VLMAX has a defined value, VLEN is a constant, + * and this form of vsetvli is defined to set vl to VLMAX. + */ + li t1, SR_VS + csrs CSR_STATUS, t1 + csrs CSR_VCSR, x0 + vsetvli t1, x0, e8, m8, ta, ma + vmv.v.i v0, 0 + vmv.v.i v8, 0 + vmv.v.i v16, 0 + vmv.v.i v24, 0 + /* note that the caller must clear SR_VS */ +#endif /* CONFIG_RISCV_ISA_V */ + .Lreset_regs_done: ret END(reset_regs)