[-next,v21,18/27] riscv: kvm: Add V extension to KVM ISA

Message ID	20230605110724.21391-19-andy.chiu@sifive.com (mailing list archive)
State	Accepted
Commit	bf78f1ea6e5108a7ebd55be0853f0716433117a9
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Subject: [PATCH -next v21 18/27] riscv: kvm: Add V extension to KVM ISA Date: Mon, 5 Jun 2023 11:07:15 +0000 Message-Id: <20230605110724.21391-19-andy.chiu@sifive.com> In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	riscv: Add vector ISA support \| expand [-next,v21,00/27] riscv: Add vector ISA support [-next,v21,01/27] riscv: Rename __switch_to_aux() -> fpu [-next,v21,02/27] riscv: Extending cpufeature.c to detect V-extension [-next,v21,03/27] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 [-next,v21,04/27] riscv: Add new csr defines related to vector extension [-next,v21,05/27] riscv: Clear vector regfile on bootup [-next,v21,06/27] riscv: Disable Vector Instructions for kernel itself [-next,v21,07/27] riscv: Introduce Vector enable/disable helpers [-next,v21,08/27] riscv: Introduce riscv_v_vsize to record size of Vector context [-next,v21,09/27] riscv: Introduce struct/helpers to save/restore per-task Vector state [-next,v21,10/27] riscv: Add task switch support for vector [-next,v21,11/27] riscv: Allocate user's vector context in the first-use trap [-next,v21,12/27] riscv: Add ptrace vector support [-next,v21,13/27] riscv: signal: check fp-reserved words unconditionally [-next,v21,14/27] riscv: signal: Add sigcontext save/restore for vector [-next,v21,15/27] riscv: signal: Report signal frame size to userspace via auxv [-next,v21,16/27] riscv: signal: validate altstack to reflect Vector [-next,v21,17/27] riscv: prevent stack corruption by reserving task_pt_regs(p) early [-next,v21,18/27] riscv: kvm: Add V extension to KVM ISA [-next,v21,19/27] riscv: KVM: Add vector lazy save/restore support [-next,v21,20/27] riscv: hwcap: change ELF_HWCAP to a function [-next,v21,21/27] riscv: Add prctl controls for userspace vector management [-next,v21,22/27] riscv: Add sysctl to set the default vector rule for new processes [-next,v21,23/27] riscv: detect assembler support for .option arch [-next,v21,24/27] riscv: Enable Vector code to be built [-next,v21,25/27] riscv: Add documentation for Vector [-next,v21,26/27] selftests: Test RISC-V Vector prctl interface [-next,v21,27/27] selftests: add .gitignore file for RISC-V hwprobe

Message ID

20230605110724.21391-19-andy.chiu@sifive.com (mailing list archive)

State

Accepted

Commit

bf78f1ea6e5108a7ebd55be0853f0716433117a9

Headers

From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org,
	palmer@dabbelt.com,
	anup@brainfault.org,
	atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org
Cc: vineetg@rivosinc.com,
	greentime.hu@sifive.com,
	guoren@linux.alibaba.com,
	Vincent Chen <vincent.chen@sifive.com>,
	Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Subject: [PATCH -next v21 18/27] riscv: kvm: Add V extension to KVM ISA
Date: Mon,  5 Jun 2023 11:07:15 +0000
Message-Id: <20230605110724.21391-19-andy.chiu@sifive.com>
In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com>
References: <20230605110724.21391-1-andy.chiu@sifive.com>
Precedence: list
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Errors-To: 
 linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org

Series

riscv: Add vector ISA support | expand

Checks

Context	Check	Description
conchuod/cover_letter	success	Series has a cover letter
conchuod/tree_selection	success	Guessed tree name to be for-next at HEAD 90502d51ab90
conchuod/fixes_present	success	Fixes tag not required for -next series
conchuod/maintainers_pattern	success	MAINTAINERS pattern errors before the patch: 6 and now 6
conchuod/verify_signedoff	success	Signed-off-by tag matches author and committer
conchuod/kdoc	success	Errors and warnings before: 0 this patch: 0
conchuod/build_rv64_clang_allmodconfig	success	Errors and warnings before: 8 this patch: 8
conchuod/module_param	success	Was 0 now: 0
conchuod/build_rv64_gcc_allmodconfig	success	Errors and warnings before: 24 this patch: 24
conchuod/build_rv32_defconfig	success	Build OK
conchuod/dtb_warn_rv64	success	Errors and warnings before: 3 this patch: 3
conchuod/header_inline	success	No static functions without inline keyword in header files
conchuod/checkpatch	success	total: 0 errors, 0 warnings, 0 checks, 14 lines checked
conchuod/build_rv64_nommu_k210_defconfig	success	Build OK
conchuod/verify_fixes	success	No Fixes tag
conchuod/build_rv64_nommu_virt_defconfig	success	Build OK

Context

Check

Description

conchuod/cover_letter

success

Series has a cover letter

conchuod/tree_selection

success

Guessed tree name to be for-next at HEAD 90502d51ab90

conchuod/fixes_present

success

Fixes tag not required for -next series

conchuod/maintainers_pattern

success

MAINTAINERS pattern errors before the patch: 6 and now 6

conchuod/verify_signedoff

success

Signed-off-by tag matches author and committer

conchuod/kdoc

success

Errors and warnings before: 0 this patch: 0

conchuod/build_rv64_clang_allmodconfig

success

Errors and warnings before: 8 this patch: 8

conchuod/module_param

success

Was 0 now: 0

conchuod/build_rv64_gcc_allmodconfig

success

Errors and warnings before: 24 this patch: 24

conchuod/build_rv32_defconfig

success

Build OK

conchuod/dtb_warn_rv64

success

Errors and warnings before: 3 this patch: 3

conchuod/header_inline

success

No static functions without inline keyword in header files

conchuod/checkpatch

success

total: 0 errors, 0 warnings, 0 checks, 14 lines checked

conchuod/build_rv64_nommu_k210_defconfig

success

Build OK

conchuod/verify_fixes

success

No Fixes tag

conchuod/build_rv64_nommu_virt_defconfig

success

Build OK

Commit Message

Andy Chiu June 5, 2023, 11:07 a.m. UTC

From: Vincent Chen <vincent.chen@sifive.com>

Add V extension to KVM isa extension list to enable supporting of V
extension on VCPUs.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
---
 arch/riscv/include/uapi/asm/kvm.h | 1 +
 arch/riscv/kvm/vcpu.c             | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index f92790c9481a..8feb57c4c2e8 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -121,6 +121,7 @@  enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_ZICBOZ,
 	KVM_RISCV_ISA_EXT_ZBB,
 	KVM_RISCV_ISA_EXT_SSAIA,
+	KVM_RISCV_ISA_EXT_V,
 	KVM_RISCV_ISA_EXT_MAX,
 };
 
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 8bd9f2a8a0b9..f3282ff371ca 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -57,6 +57,7 @@  static const unsigned long kvm_isa_ext_arr[] = {
 	[KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h,
 	[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
 	[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
+	[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
 
 	KVM_ISA_EXT_ARR(SSAIA),
 	KVM_ISA_EXT_ARR(SSTC),

[-next,v21,18/27] riscv: kvm: Add V extension to KVM ISA

Checks

Commit Message

Patch