Message ID | 20230626172608.2978505-1-samuel.holland@sifive.com (mailing list archive) |
---|---|
State | Handled Elsewhere |
Headers | show |
Series | gpio: sifive: Support IRQ wake | expand |
Context | Check | Description |
---|---|---|
conchuod/cover_letter | success | Single patches do not need cover letters |
conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 488833ccdcac |
conchuod/fixes_present | success | Fixes tag not required for -next series |
conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
conchuod/module_param | success | Was 0 now: 0 |
conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
conchuod/build_rv32_defconfig | success | Build OK |
conchuod/dtb_warn_rv64 | success | Errors and warnings before: 20 this patch: 20 |
conchuod/header_inline | success | No static functions without inline keyword in header files |
conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 7 lines checked |
conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
conchuod/verify_fixes | success | No Fixes tag |
conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Mon, Jun 26, 2023 at 7:26 PM Samuel Holland <samuel.holland@sifive.com> wrote: > > Each pin drives a separate interrupt in the parent IRQ domain, so there > is no need to set IRQCHIP_MASK_ON_SUSPEND. > > Signed-off-by: Samuel Holland <samuel.holland@sifive.com> > --- > > drivers/gpio/gpio-sifive.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c > index 98939cd4a71e..c2653313f3a2 100644 > --- a/drivers/gpio/gpio-sifive.c > +++ b/drivers/gpio/gpio-sifive.c > @@ -150,6 +150,7 @@ static const struct irq_chip sifive_gpio_irqchip = { > .irq_disable = sifive_gpio_irq_disable, > .irq_eoi = sifive_gpio_irq_eoi, > .irq_set_affinity = sifive_gpio_irq_set_affinity, > + .irq_set_wake = irq_chip_set_wake_parent, > .flags = IRQCHIP_IMMUTABLE, > GPIOCHIP_IRQ_RESOURCE_HELPERS, > }; > -- > 2.40.1 > Applied, thanks! Bart
diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c index 98939cd4a71e..c2653313f3a2 100644 --- a/drivers/gpio/gpio-sifive.c +++ b/drivers/gpio/gpio-sifive.c @@ -150,6 +150,7 @@ static const struct irq_chip sifive_gpio_irqchip = { .irq_disable = sifive_gpio_irq_disable, .irq_eoi = sifive_gpio_irq_eoi, .irq_set_affinity = sifive_gpio_irq_set_affinity, + .irq_set_wake = irq_chip_set_wake_parent, .flags = IRQCHIP_IMMUTABLE, GPIOCHIP_IRQ_RESOURCE_HELPERS, };
Each pin drives a separate interrupt in the parent IRQ domain, so there is no need to set IRQCHIP_MASK_ON_SUSPEND. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- drivers/gpio/gpio-sifive.c | 1 + 1 file changed, 1 insertion(+)