| Message ID | 20231019135905.3658215-1-peterlin@andestech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Support Andes PMU extension | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On 19/10/2023 15:59, Yu Chien Peter Lin wrote: > Add "andestech,cpu-intc" compatible string for Andes INTC which > provides Andes-specific IRQ chip functions. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > --- > Changes v1 -> v2: > - New patch > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 97e8441eda1c..5b216e11c69f 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -99,7 +99,9 @@ properties: > const: 1 > > compatible: > - const: riscv,cpu-intc > + enum: > + - riscv,cpu-intc > + - andestech,cpu-intc Keep alphabetical order. Do not add stuff to the end of the lists. This is a generic rule. Everywhere. Best regards, Krzysztof
On Fri, Oct 20, 2023 at 09:00:03AM +0200, Krzysztof Kozlowski wrote: > On 19/10/2023 15:59, Yu Chien Peter Lin wrote: > > Add "andestech,cpu-intc" compatible string for Andes INTC which > > provides Andes-specific IRQ chip functions. > > > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > > --- > > Changes v1 -> v2: > > - New patch > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index 97e8441eda1c..5b216e11c69f 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -99,7 +99,9 @@ properties: > > const: 1 > > > > compatible: > > - const: riscv,cpu-intc > > + enum: > > + - riscv,cpu-intc > > + - andestech,cpu-intc > > Keep alphabetical order. Do not add stuff to the end of the lists. This > is a generic rule. Everywhere. Hi Krzysztof, Thansk for pointing this out. Will fix this in PATCH v3. Best regards, Peter Lin > Best regards, > Krzysztof >
Yo, On Thu, Oct 19, 2023 at 09:59:05PM +0800, Yu Chien Peter Lin wrote: > Add "andestech,cpu-intc" compatible string for Andes INTC which > provides Andes-specific IRQ chip functions. You need to provide some information as to what differentiates your intc from the regular one, not mention linux driver specifics. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > --- > Changes v1 -> v2: > - New patch > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 97e8441eda1c..5b216e11c69f 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -99,7 +99,9 @@ properties: > const: 1 > > compatible: > - const: riscv,cpu-intc > + enum: > + - riscv,cpu-intc > + - andestech,cpu-intc Should the andestech intc not fall back to the generic intc compatible? The generic one appears to implement a compatible subset of the features that yours does. Cheers, Conor. > > interrupt-controller: true > > -- > 2.34.1 > >
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 97e8441eda1c..5b216e11c69f 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -99,7 +99,9 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + enum: + - riscv,cpu-intc + - andestech,cpu-intc interrupt-controller: true
Add "andestech,cpu-intc" compatible string for Andes INTC which provides Andes-specific IRQ chip functions. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> --- Changes v1 -> v2: - New patch --- Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)