| Message ID | 20231023082911.23242-13-luxu.kernel@bytedance.com (mailing list archive) |
|---|---|
| State | RFC |
| Headers | show |
| Series | riscv: Introduce Pseudo NMI | expand |
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 487e4293f31e..ecccdc91563f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -672,7 +672,7 @@ config RISCV_BOOT_SPINWAIT config RISCV_PSEUDO_NMI bool "Support for NMI-like interrupts" depends on !RISCV_M_MODE - default n + default y help Adds support for mimicking Non-Maskable Interrupts through the use of CSR_IE register.
This commit enables CONFIG_RISCV_PSEUDO_NMI in default. Now pseudo NMI feature is defaultly enabled on RISC-V. Signed-off-by: Xu Lu <luxu.kernel@bytedance.com> --- arch/riscv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)