| Message ID | 20231227175739.1453782-1-samuel.holland@sifive.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | b4070c2a242e6bdd9d355d18b8c589d9778a6fd8 |
| Headers | show |
| Series | dt-bindings: riscv: cpus: Clarify mmu-type interpretation | expand |
On Wed, Dec 27, 2023 at 09:57:38AM -0800, Samuel Holland wrote: > The current description implies that only a single address translation > mode is available to the operating system. However, some implementations > support multiple address translation modes, and the operating system is > free to choose between them. > > Per the RISC-V privileged specification, Sv48 implementations must also > implement Sv39, and likewise Sv57 implies support for Sv48. This means > it is possible to describe all supported address translation modes using > a single value, by naming the largest supported mode. This appears to > have been the intended usage of the property, so note it explicitly. > > Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema") > Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
Hello: This patch was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Wed, 27 Dec 2023 09:57:38 -0800 you wrote: > The current description implies that only a single address translation > mode is available to the operating system. However, some implementations > support multiple address translation modes, and the operating system is > free to choose between them. > > Per the RISC-V privileged specification, Sv48 implementations must also > implement Sv39, and likewise Sv57 implies support for Sv48. This means > it is possible to describe all supported address translation modes using > a single value, by naming the largest supported mode. This appears to > have been the intended usage of the property, so note it explicitly. > > [...] Here is the summary with links: - dt-bindings: riscv: cpus: Clarify mmu-type interpretation https://git.kernel.org/riscv/c/b4070c2a242e You are awesome, thank you!
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index f392e367d673..f166c729c482 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -62,8 +62,8 @@ properties: mmu-type: description: - Identifies the MMU address translation mode used on this - hart. These values originate from the RISC-V Privileged + Identifies the largest MMU address translation mode supported by + this hart. These values originate from the RISC-V Privileged Specification document, available from https://riscv.org/specifications/ $ref: /schemas/types.yaml#/definitions/string
The current description implies that only a single address translation mode is available to the operating system. However, some implementations support multiple address translation modes, and the operating system is free to choose between them. Per the RISC-V privileged specification, Sv48 implementations must also implement Sv39, and likewise Sv57 implies support for Sv48. This means it is possible to describe all supported address translation modes using a single value, by naming the largest supported mode. This appears to have been the intended usage of the property, so note it explicitly. Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)