| Message ID | 20240216000837.1868917-6-samuel.holland@sifive.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | SiFive cache controller PMU drivers | expand |
On 16/02/2024 01:08, Samuel Holland wrote: > From: Eric Lin <eric.lin@sifive.com> > > Add YAML DT binding documentation for the SiFive Private L2 Cache > controller. Some functionality and the corresponding register bits were > removed in the sifive,pl2cache1 version of the hardware, which creates > the unusual situation where the newer hardware's compatible string is > the fallback for the older one. > > Signed-off-by: Eric Lin <eric.lin@sifive.com> > Co-developed-by: Samuel Holland <samuel.holland@sifive.com> > Signed-off-by: Samuel Holland <samuel.holland@sifive.com> > --- > > Changes in v1: > - Add back select: clause to binding > - Make sifive,pl2cache1 the fallback for sifive,pl2cache0 > - Fix the order of the reg property declaration > - Document the sifive,perfmon-counters property This is no v1. Please implement entire feedback from previous v2, v3 or whatever it was and reference old posting or continue the numbering. Best regards, Krzysztof
Hi Krzysztof, On 2024-02-17 3:12 AM, Krzysztof Kozlowski wrote: > On 16/02/2024 01:08, Samuel Holland wrote: >> From: Eric Lin <eric.lin@sifive.com> >> >> Add YAML DT binding documentation for the SiFive Private L2 Cache >> controller. Some functionality and the corresponding register bits were >> removed in the sifive,pl2cache1 version of the hardware, which creates >> the unusual situation where the newer hardware's compatible string is >> the fallback for the older one. >> >> Signed-off-by: Eric Lin <eric.lin@sifive.com> >> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> >> --- >> >> Changes in v1: >> - Add back select: clause to binding >> - Make sifive,pl2cache1 the fallback for sifive,pl2cache0 >> - Fix the order of the reg property declaration >> - Document the sifive,perfmon-counters property > > This is no v1. Please implement entire feedback from previous v2, v3 or > whatever it was and reference old posting or continue the numbering. The old posting is referenced in the cover letter: This series is a follow-up to Eric Lin's series "[PATCH v2 0/3] Add SiFive Private L2 cache and PMU driver": https://lore.kernel.org/linux-riscv/20230720135125.21240-1-eric.lin@sifive.com/ So these changes include implementation of the feedback from that v2. Regards, Samuel
diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache0.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache0.yaml new file mode 100644 index 000000000000..d89e2e5d0a97 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache0.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023-2024 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/sifive,pl2cache0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Private L2 Cache Controller + +maintainers: + - Eric Lin <eric.lin@sifive.com> + +description: + The SiFive Private L2 Cache Controller is a per-core cache which communicates + with both the upstream L1 caches and downstream L3 cache or memory, enabling a + high-performance cache subsystem. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +select: + properties: + compatible: + contains: + enum: + - sifive,pl2cache1 + + required: + - compatible + +properties: + compatible: + oneOf: + - items: + - const: sifive,pl2cache0 + - const: sifive,pl2cache1 + - const: cache + - items: + - const: sifive,pl2cache1 + - const: cache + + reg: + maxItems: 1 + + cache-block-size: true + cache-level: true + cache-sets: true + cache-size: true + cache-unified: true + + next-level-cache: true + + sifive,perfmon-counters: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: Number of PMU counter registers + +required: + - compatible + - reg + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +additionalProperties: false + +examples: + - | + cache-controller@10104000 { + compatible = "sifive,pl2cache1", "cache"; + reg = <0x10104000 0x4000>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + next-level-cache = <&L4>; + sifive,perfmon-counters = <6>; + };