| Message ID | 20240605205658.184399-4-samuel.holland@sifive.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: Per-thread envcfg CSR support | expand |
On Wed, Jun 05, 2024 at 01:56:47PM -0700, Samuel Holland wrote: >Now that the [ms]envcfg CSR value is maintained per thread, not per >hart, riscv_user_isa_enable() only needs to be called once during boot, >to set the value for the init task. This also allows it to be marked as >__init. riscv_isa_extension_check() sets any_cpu_has_zicboz, so it also >needs to be marked __init; it could have had this annotation already. > >Signed-off-by: Samuel Holland <samuel.holland@sifive.com> >--- > > arch/riscv/include/asm/cpufeature.h | 2 +- > arch/riscv/kernel/cpufeature.c | 8 ++++---- > arch/riscv/kernel/smpboot.c | 2 -- > 3 files changed, 5 insertions(+), 7 deletions(-) > >diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h >index 347805446151..4bf7b7ebf6b3 100644 >--- a/arch/riscv/include/asm/cpufeature.h >+++ b/arch/riscv/include/asm/cpufeature.h >@@ -31,7 +31,7 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > /* Per-cpu ISA extensions. */ > extern struct riscv_isainfo hart_isa[NR_CPUS]; > >-void riscv_user_isa_enable(void); >+void __init riscv_user_isa_enable(void); > > #if defined(CONFIG_RISCV_MISALIGNED) > bool check_unaligned_access_emulated_all_cpus(void); >diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >index 1153b96346ae..bfe8550c0aae 100644 >--- a/arch/riscv/kernel/cpufeature.c >+++ b/arch/riscv/kernel/cpufeature.c >@@ -27,7 +27,7 @@ > > #define NUM_ALPHA_EXTS ('z' - 'a' + 1) > >-static bool any_cpu_has_zicboz; >+static bool any_cpu_has_zicboz __initdata; > > unsigned long elf_hwcap __read_mostly; > >@@ -74,7 +74,7 @@ bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned i > } > EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); > >-static bool riscv_isa_extension_check(int id) >+static bool __init riscv_isa_extension_check(int id) > { > switch (id) { > case RISCV_ISA_EXT_ZICBOM: >@@ -725,12 +725,12 @@ unsigned long riscv_get_elf_hwcap(void) > return hwcap; > } > >-void riscv_user_isa_enable(void) >+void __init riscv_user_isa_enable(void) > { > if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) > current->thread.envcfg |= ENVCFG_CBZE; > else if (any_cpu_has_zicboz) >- pr_warn_once("Zicboz disabled as it is unavailable on some harts\n"); >+ pr_warn("Zicboz disabled as it is unavailable on some harts\n"); > } > > #ifdef CONFIG_RISCV_ALTERNATIVE >diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c >index 1319b29ce3b5..3e8ece31c30d 100644 >--- a/arch/riscv/kernel/smpboot.c >+++ b/arch/riscv/kernel/smpboot.c >@@ -231,8 +231,6 @@ asmlinkage __visible void smp_callin(void) > elf_hwcap &= ~COMPAT_HWCAP_ISA_V; > } > >- riscv_user_isa_enable(); >- > /* > * Remote cache and TLB flushes are ignored while the CPU is offline, > * so flush them both right now just in case. Suggestion: Squash with current patch 1 and call it patch 2. >-- >2.44.1 >
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 347805446151..4bf7b7ebf6b3 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -31,7 +31,7 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; -void riscv_user_isa_enable(void); +void __init riscv_user_isa_enable(void); #if defined(CONFIG_RISCV_MISALIGNED) bool check_unaligned_access_emulated_all_cpus(void); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1153b96346ae..bfe8550c0aae 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -27,7 +27,7 @@ #define NUM_ALPHA_EXTS ('z' - 'a' + 1) -static bool any_cpu_has_zicboz; +static bool any_cpu_has_zicboz __initdata; unsigned long elf_hwcap __read_mostly; @@ -74,7 +74,7 @@ bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned i } EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); -static bool riscv_isa_extension_check(int id) +static bool __init riscv_isa_extension_check(int id) { switch (id) { case RISCV_ISA_EXT_ZICBOM: @@ -725,12 +725,12 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } -void riscv_user_isa_enable(void) +void __init riscv_user_isa_enable(void) { if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) current->thread.envcfg |= ENVCFG_CBZE; else if (any_cpu_has_zicboz) - pr_warn_once("Zicboz disabled as it is unavailable on some harts\n"); + pr_warn("Zicboz disabled as it is unavailable on some harts\n"); } #ifdef CONFIG_RISCV_ALTERNATIVE diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 1319b29ce3b5..3e8ece31c30d 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -231,8 +231,6 @@ asmlinkage __visible void smp_callin(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_V; } - riscv_user_isa_enable(); - /* * Remote cache and TLB flushes are ignored while the CPU is offline, * so flush them both right now just in case.
Now that the [ms]envcfg CSR value is maintained per thread, not per hart, riscv_user_isa_enable() only needs to be called once during boot, to set the value for the init task. This also allows it to be marked as __init. riscv_isa_extension_check() sets any_cpu_has_zicboz, so it also needs to be marked __init; it could have had this annotation already. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- arch/riscv/include/asm/cpufeature.h | 2 +- arch/riscv/kernel/cpufeature.c | 8 ++++---- arch/riscv/kernel/smpboot.c | 2 -- 3 files changed, 5 insertions(+), 7 deletions(-)