| Message ID | 20250410152519.1358964-11-pinkesh.vaghela@einfochips.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | Basic device tree support for ESWIN EIC7700 RISC-V SoC | expand |
| Context | Check | Description |
|---|---|---|
| bjorn/pre-ci_am | success | Success |
| bjorn/build-rv32-defconfig | success | build-rv32-defconfig |
| bjorn/build-rv64-clang-allmodconfig | success | build-rv64-clang-allmodconfig |
| bjorn/build-rv64-gcc-allmodconfig | success | build-rv64-gcc-allmodconfig |
| bjorn/build-rv64-nommu-k210-defconfig | success | build-rv64-nommu-k210-defconfig |
| bjorn/build-rv64-nommu-k210-virt | success | build-rv64-nommu-k210-virt |
| bjorn/checkpatch | warning | checkpatch |
| bjorn/dtb-warn-rv64 | success | dtb-warn-rv64 |
| bjorn/header-inline | success | header-inline |
| bjorn/kdoc | success | kdoc |
| bjorn/module-param | success | module-param |
| bjorn/verify-fixes | success | verify-fixes |
| bjorn/verify-signedoff | success | verify-signedoff |
Hi Pinkesh, On 4/10/25 12:25 PM, Pinkesh Vaghela wrote: > From: Min Lin <linmin@eswincomputing.com> > > Add initial board data for HiFive Premier P550 Development board > > Currently the data populated in this DT file describes the board > DRAM configuration, UART and GPIO. > > Signed-off-by: Min Lin <linmin@eswincomputing.com> > Co-developed-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > Tested-by: Samuel Holland <samuel.holland@sifive.com> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/eswin/Makefile | 2 ++ > .../dts/eswin/eic7700-hifive-premier-p550.dts | 29 +++++++++++++++++++ > 3 files changed, 32 insertions(+) > create mode 100644 arch/riscv/boot/dts/eswin/Makefile > create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index 64a898da9aee..29a97a663ea2 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > subdir-y += allwinner > subdir-y += canaan > +subdir-y += eswin > subdir-y += microchip > subdir-y += renesas > subdir-y += sifive > diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile > new file mode 100644 > index 000000000000..224101ae471e > --- /dev/null > +++ b/arch/riscv/boot/dts/eswin/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_ESWIN) += eic7700-hifive-premier-p550.dtb > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts > new file mode 100644 > index 000000000000..131ed1fc6b2e > --- /dev/null > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts > @@ -0,0 +1,29 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2024, Beijing ESWIN Computing Technology Co., Ltd. > + */ > + > +/dts-v1/; > + > +#include "eic7700.dtsi" > + > +/ { > + compatible = "sifive,hifive-premier-p550", "eswin,eic7700"; > + model = "SiFive HiFive Premier P550"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&uart2 { > + status = "okay"; > +}; Although commit log says that this includes DRAM configuration, looks like it's missing? In order to test this patchset, had to add this following memory definition (picked from vendor kernel repository): L50: memory@80000000 { compatible = "sifive,axi4-mem-port", "sifive,axi4-port", "sifive,mem-port"; device_type = "memory"; reg = <0x0 0x80000000 0x7f 0x80000000>; sifive,port-width-bytes = <32>; }; Regards,
Hi Ariel, On 2025-04-14 7:55 AM, Ariel D'Alessandro wrote: > Hi Pinkesh, > > On 4/10/25 12:25 PM, Pinkesh Vaghela wrote: >> From: Min Lin <linmin@eswincomputing.com> >> >> Add initial board data for HiFive Premier P550 Development board >> >> Currently the data populated in this DT file describes the board >> DRAM configuration, UART and GPIO. >> >> Signed-off-by: Min Lin <linmin@eswincomputing.com> >> Co-developed-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> >> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> >> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> >> Tested-by: Samuel Holland <samuel.holland@sifive.com> >> --- >> arch/riscv/boot/dts/Makefile | 1 + >> arch/riscv/boot/dts/eswin/Makefile | 2 ++ >> .../dts/eswin/eic7700-hifive-premier-p550.dts | 29 +++++++++++++++++++ >> 3 files changed, 32 insertions(+) >> create mode 100644 arch/riscv/boot/dts/eswin/Makefile >> create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts >> >> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile >> index 64a898da9aee..29a97a663ea2 100644 >> --- a/arch/riscv/boot/dts/Makefile >> +++ b/arch/riscv/boot/dts/Makefile >> @@ -1,6 +1,7 @@ >> # SPDX-License-Identifier: GPL-2.0 >> subdir-y += allwinner >> subdir-y += canaan >> +subdir-y += eswin >> subdir-y += microchip >> subdir-y += renesas >> subdir-y += sifive >> diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/ >> Makefile >> new file mode 100644 >> index 000000000000..224101ae471e >> --- /dev/null >> +++ b/arch/riscv/boot/dts/eswin/Makefile >> @@ -0,0 +1,2 @@ >> +# SPDX-License-Identifier: GPL-2.0 >> +dtb-$(CONFIG_ARCH_ESWIN) += eic7700-hifive-premier-p550.dtb >> diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/ >> riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts >> new file mode 100644 >> index 000000000000..131ed1fc6b2e >> --- /dev/null >> +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts >> @@ -0,0 +1,29 @@ >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >> +/* >> + * Copyright (c) 2024, Beijing ESWIN Computing Technology Co., Ltd. >> + */ >> + >> +/dts-v1/; >> + >> +#include "eic7700.dtsi" >> + >> +/ { >> + compatible = "sifive,hifive-premier-p550", "eswin,eic7700"; >> + model = "SiFive HiFive Premier P550"; >> + >> + aliases { >> + serial0 = &uart0; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> +}; >> + >> +&uart0 { >> + status = "okay"; >> +}; >> + >> +&uart2 { >> + status = "okay"; >> +}; > > Although commit log says that this includes DRAM configuration, looks like it's > missing? In order to test this patchset, had to add this following memory > definition (picked from vendor kernel repository): > > L50: memory@80000000 { > compatible = "sifive,axi4-mem-port", "sifive,axi4-port", > "sifive,mem-port"; > device_type = "memory"; > reg = <0x0 0x80000000 0x7f 0x80000000>; > sifive,port-width-bytes = <32>; > }; That is a misstatement in the commit message. The memory node is not included in the static devicetree because the amount of RAM installed on the board is variable. It is the responsibility of firmware to provide the memory map, either through EFI or by patching the memory node into the DT at runtime. I believe the current BSP U-Boot does the former but not the latter. Regards, Samuel
Hey, On Mon, 2025-04-14 at 11:00 -0500, Samuel Holland wrote: > Hi Ariel, > > On 2025-04-14 7:55 AM, Ariel D'Alessandro wrote: > > Hi Pinkesh, > > > > On 4/10/25 12:25 PM, Pinkesh Vaghela wrote: > > > From: Min Lin <linmin@eswincomputing.com> > > <snip> > > Although commit log says that this includes DRAM configuration, looks like > > it's > > missing? In order to test this patchset, had to add this following memory > > definition (picked from vendor kernel repository): > > > > L50: memory@80000000 { > > compatible = "sifive,axi4-mem-port", "sifive,axi4-port", > > "sifive,mem-port"; > > device_type = "memory"; > > reg = <0x0 0x80000000 0x7f 0x80000000>; > > sifive,port-width-bytes = <32>; > > }; > > That is a misstatement in the commit message. The memory node is not included > in > the static devicetree because the amount of RAM installed on the board is > variable. It is the responsibility of firmware to provide the memory map, > either > through EFI or by patching the memory node into the DT at runtime. I believe > the > current BSP U-Boot does the former but not the latter. Amount of RAM being variable is pretty common on devices using FDT these days; Typically the dts still gets a memory node that's a reasonable default, with the expectation that e.g. u-boot will fix it up. If you look at other risc-v devicetrees in upstream they (almost?) all come with a pre-defined memory node. For the P550 board a default memory node for 16G ram seems reasonable (as that seems the minimal SKU?) That all being said. Indeed the sifive BSP u-boot doesn't seem to call the relevant `fdt_fixup_memory` to fixup the memory node, hence us having issues booting with u-boot directly (without going through EFI). Honestly this was a bit of a surprise to me as only most other architectures that's just done by common code, but that doesn't seem to be the case for risc-v (either upstream or downstream)
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 64a898da9aee..29a97a663ea2 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += allwinner subdir-y += canaan +subdir-y += eswin subdir-y += microchip subdir-y += renesas subdir-y += sifive diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile new file mode 100644 index 000000000000..224101ae471e --- /dev/null +++ b/arch/riscv/boot/dts/eswin/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ESWIN) += eic7700-hifive-premier-p550.dtb diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts new file mode 100644 index 000000000000..131ed1fc6b2e --- /dev/null +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024, Beijing ESWIN Computing Technology Co., Ltd. + */ + +/dts-v1/; + +#include "eic7700.dtsi" + +/ { + compatible = "sifive,hifive-premier-p550", "eswin,eic7700"; + model = "SiFive HiFive Premier P550"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +};