[15/17] riscv: Add V extension to KVM ISA allow list

Message ID	CAM2SziWWP8U5qs3BFh5uZjGLV6EFKSzALQ9-fsCd=wRgxy_HPw@mail.gmail.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> MIME-Version: 1.0 From: Chris Stillson <stillson@rivosinc.com> Date: Wed, 21 Sep 2022 09:50:17 -0700 Message-ID: <CAM2SziWWP8U5qs3BFh5uZjGLV6EFKSzALQ9-fsCd=wRgxy_HPw@mail.gmail.com> Subject: [PATCH 15/17] riscv: Add V extension to KVM ISA allow list To: linux-riscv@lists.infradead.org Cc: palmer@dabbelt.com Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	Prctl to enable vector commands, previous vector patches rebased \| expand [00/17] Prctl to enable vector commands, previous vector patches rebased [01/17] riscv: Rename __switch_to_aux -> fpu [02/17] riscv: Extending cpufeature.c to detect V-extension [03/17] riscv: Add new csr defines related to vector extension [04/17] riscv: Add vector feature to compile [05/17] riscv: Add has_vector/riscv_vsize to save vector features. [06/17] riscv: Reset vector register [07/17] riscv: Add vector struct and assembler definitions [08/17] riscv: Add task switch support for vector [09/17] riscv: Add ptrace vector support [10/17] riscv: Add sigcontext save/restore for vector [11/17] riscv: signal: Report signal frame size to userspace via auxv [12/17] riscv: Add support for kernel mode vector [13/17] riscv: Add vector extension XOR implementation [14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux [15/17] riscv: Add V extension to KVM ISA allow list [16/17] riscv: KVM: Add vector lazy save/restore support [17/17] riscv: prctl to enable vector commands

Message ID

CAM2SziWWP8U5qs3BFh5uZjGLV6EFKSzALQ9-fsCd=wRgxy_HPw@mail.gmail.com (mailing list archive)

State

Superseded

Headers

MIME-Version: 1.0
From: Chris Stillson <stillson@rivosinc.com>
Date: Wed, 21 Sep 2022 09:50:17 -0700
Message-ID: 
 <CAM2SziWWP8U5qs3BFh5uZjGLV6EFKSzALQ9-fsCd=wRgxy_HPw@mail.gmail.com>
Subject: [PATCH 15/17] riscv: Add V extension to KVM ISA allow list
To: linux-riscv@lists.infradead.org
Cc: palmer@dabbelt.com
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Series

Prctl to enable vector commands, previous vector patches rebased | expand

Commit Message

Chris Stillson Sept. 21, 2022, 4:50 p.m. UTC

Add V extension to KVM_RISCV_ISA_ALLOWED list to enable VCPU
to support V extension.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 1 file changed, 1 insertion(+)

--
2.25.1

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 6f59ec64175e..b242ed155262 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -35,6 +35,7 @@  extern unsigned long elf_hwcap;
 #define RISCV_ISA_EXT_m                ('m' - 'a')
 #define RISCV_ISA_EXT_s                ('s' - 'a')
 #define RISCV_ISA_EXT_u                ('u' - 'a')
+#define RISCV_ISA_EXT_v                ('v' - 'a')

 /*
  * Increse this to higher value as kernel support more ISA extensions.

[15/17] riscv: Add V extension to KVM ISA allow list

Commit Message

Patch