| Message ID | 1552431636-31511-7-git-send-email-fenghua.yu@intel.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Johannes Berg |
| Headers | show |
| Series | x86/split_lock: Enable #AC exception for split locked accesses | expand |
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ca5bc0eacb95..f65ef6f783d2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -59,6 +59,9 @@ #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) +#define MSR_IA32_CORE_CAPABILITY 0x000000cf +#define CORE_CAP_SPLIT_LOCK_DETECT BIT(5) /* Detect split lock */ + #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26)
A new IA32_CORE_CAPABILITY MSR (0xCF) is defined. Each bit in the MSR enumerates a model specific feature. Currently bit 5 enumerates #AC exception for split locked accesses. When bit 5 is 1, split locked accesses will generate #AC exception. When bit 5 is 0, split locked accesses will not generate #AC exception. Please check the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference for more detailed information on the MSR and the split lock bit. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+)