| Message ID | 1552431636-31511-9-git-send-email-fenghua.yu@intel.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Johannes Berg |
| Headers | show |
| Series | x86/split_lock: Enable #AC exception for split locked accesses | expand |
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index f65ef6f783d2..25fa808de9e2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -39,6 +39,10 @@ /* Intel MSRs. Some also available on other CPUs */ +#define MSR_TEST_CTL 0x00000033 +#define TEST_CTL_ENABLE_SPLIT_LOCK_DETECT_SHIFT 29 +#define TEST_CTL_ENABLE_SPLIT_LOCK_DETECT BIT(29) + #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ #define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
Setting bit 29 in MSR TEST_CTL register 0x33 enables split lock issue detection and clearing the bit disables split lock issue detection. Define the MSR and the bit. The definitions will be used in enabling or disabling split lock detection. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> --- arch/x86/include/asm/msr-index.h | 4 ++++ 1 file changed, 4 insertions(+)