Show patches with: Series = target/riscv: support packed extension v0.9.2       |    State = Action Required       |   38 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[38/38] target/riscv: configure and turn on packed extension from command line target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[37/38] target/riscv: RV64 Only 32-bit Packing Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[33/38] target/riscv: RV64 Only 32-bit Multiply Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[28/38] target/riscv: Non-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[27/38] target/riscv: 32-bit Computation Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[22/38] target/riscv: 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[20/38] target/riscv: Partial-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
[19/38] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
[16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[15/38] target/riscv: 16-bit Packing Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
[14/38] target/riscv: 8-bit Unpacking Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
[13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
[12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
[11/38] target/riscv: SIMD 8-bit Multiply Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
[10/38] target/riscv: SIMD 16-bit Multiply Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[09/38] target/riscv: SIMD 8-bit Compare Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
[08/38] target/riscv: SIMD 16-bit Compare Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
[07/38] target/riscv: SIMD 8-bit Shift Instructions target/riscv: support packed extension v0.9.2 1 1 - --- 2021-02-12 LIU Zhiwei New
[06/38] target/riscv: SIMD 16-bit Shift Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[05/38] target/riscv: 8-bit Addition & Subtraction Instruction target/riscv: support packed extension v0.9.2 1 1 - --- 2021-02-12 LIU Zhiwei New
[04/38] target/riscv: 16-bit Addition & Subtraction Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[03/38] target/riscv: Fixup saturate subtract function target/riscv: support packed extension v0.9.2 - 2 - --- 2021-02-12 LIU Zhiwei New
[02/38] target/riscv: Hoist vector functions target/riscv: support packed extension v0.9.2 - 1 - --- 2021-02-12 LIU Zhiwei New
[01/38] target/riscv: implementation-defined constant parameters target/riscv: support packed extension v0.9.2 - 1 - --- 2021-02-12 LIU Zhiwei New