diff mbox series

[4/6] target/m68k: Optimize get_sr() using deposit_i32()

Message ID 20190310003428.11723-5-f4bug@amsat.org (mailing list archive)
State New, archived
Headers show
Series target/m68k: Optimize few instructions using deposit/extraxt_i32() | expand

Commit Message

Philippe Mathieu-Daudé March 10, 2019, 12:34 a.m. UTC 
Doing so we free one tcg_temp.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/m68k/translate.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

Comments

Richard Henderson March 11, 2019, 2:52 p.m. UTC | #1 
On 3/9/19 4:34 PM, Philippe Mathieu-Daudé wrote:
>  static TCGv gen_get_sr(DisasContext *s)
>  {
> -    TCGv ccr;
> -    TCGv sr;
> +    TCGv dest;
>  
> -    ccr = gen_get_ccr(s);
> -    sr = tcg_temp_new();
> -    tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
> -    tcg_gen_or_i32(sr, sr, ccr);
> -    tcg_temp_free(ccr);
> -    return sr;
> +    dest = gen_get_ccr(s);
> +    tcg_gen_deposit_i32(dest, dest, QREG_SR, 5, 11);
> +    return dest;

Err.. there's no shift of QREG_SR by 5 in the original.
I think you meant

  tcg_gen_deposit_i32(dest, QREG_SR, dest, 0, 5);

But I'd be surprised if QREG_SR even has those bits set,
and we could elide the ANDI entirely, making this just an OR.


r~
diff mbox series

Patch

diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index ea95d55a11..f43ac07b7f 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2217,15 +2217,11 @@  static TCGv gen_get_ccr(DisasContext *s)
 
 static TCGv gen_get_sr(DisasContext *s)
 {
-    TCGv ccr;
-    TCGv sr;
+    TCGv dest;
 
-    ccr = gen_get_ccr(s);
-    sr = tcg_temp_new();
-    tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
-    tcg_gen_or_i32(sr, sr, ccr);
-    tcg_temp_free(ccr);
-    return sr;
+    dest = gen_get_ccr(s);
+    tcg_gen_deposit_i32(dest, dest, QREG_SR, 5, 11);
+    return dest;
 }
 
 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)