| Message ID | 20210110081429.10126-4-bmeng.cn@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/ssi: imx_spi: Fix various bugs in the imx_spi model | expand |
On 1/10/21 9:14 AM, Bin Meng wrote: > From: Xuzhou Cheng <xuzhou.cheng@windriver.com> > > When a write to ECSPI_CONREG register to disable the SPI controller, > imx_spi_reset() is called to reset the controller, but chip select > lines should have been disabled, otherwise the state machine of any > devices (e.g.: SPI flashes) connected to the SPI master is stuck to > its last state and responds incorrectly to any follow-up commands. > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > --- > > (no changes since v3) > > Changes in v3: > - Move the chip selects disable out of imx_spi_reset() > > Changes in v2: > - Fix the "Fixes" tag in the commit message > > hw/ssi/imx_spi.c | 6 ++++++ > 1 file changed, 6 insertions(+) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 2c4c5ec1b8..168ea95440 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -246,9 +246,15 @@ static void imx_spi_reset(DeviceState *dev) static void imx_spi_hard_reset(IMXSPIState *s) { + int i; + imx_spi_reset(DEVICE(s)); imx_spi_update_irq(s); + + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)