diff mbox series

[v6,10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

Message ID 20210112093950.17530-11-frank.chang@sifive.com (mailing list archive)
State New, archived
Headers show
Series support vector extension v1.0 | expand

Commit Message

Frank Chang Jan. 12, 2021, 9:38 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/csr.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Alistair Francis Jan. 19, 2021, 5:40 p.m. UTC | #1 
On Tue, Jan 12, 2021 at 2:03 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> If VS field is off, accessing vector csr registers should raise an
> illegal-instruction exception.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 7a6554447af..30f1593efb1 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -56,6 +56,11 @@ static int fs(CPURISCVState *env, int csrno)
>  static int vs(CPURISCVState *env, int csrno)
>  {
>      if (env->misa & RVV) {
> +#if !defined(CONFIG_USER_ONLY)
> +        if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
> +            return -1;
> +        }
> +#endif
>          return 0;
>      }
>      return -1;
> --
> 2.17.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7a6554447af..30f1593efb1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -56,6 +56,11 @@  static int fs(CPURISCVState *env, int csrno)
 static int vs(CPURISCVState *env, int csrno)
 {
     if (env->misa & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+        if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+            return -1;
+        }
+#endif
         return 0;
     }
     return -1;