| Message ID | 20210112093950.17530-69-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support vector extension v1.0 | expand |
On Tue, Jan 12, 2021 at 2:50 AM <frank.chang@sifive.com> wrote: > > From: Hsiangkai Wang <kai.wang@sifive.com> > > Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com> > Acked-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Frank Chang <frank.chang@sifive.com> This patch won't apply any more, we have removed the hardcoded GDB register list. Alistair > --- > gdb-xml/riscv-32bit-csr.xml | 11 ++++++----- > gdb-xml/riscv-64bit-csr.xml | 11 ++++++----- > target/riscv/gdbstub.c | 4 ++-- > 3 files changed, 14 insertions(+), 12 deletions(-) > > diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml > index da1bf19e2f4..3d2031da7dc 100644 > --- a/gdb-xml/riscv-32bit-csr.xml > +++ b/gdb-xml/riscv-32bit-csr.xml > @@ -110,6 +110,8 @@ > <reg name="mcause" bitsize="32"/> > <reg name="mtval" bitsize="32"/> > <reg name="mip" bitsize="32"/> > + <reg name="mtinst" bitsize="32"/> > + <reg name="mtval2" bitsize="32"/> > <reg name="pmpcfg0" bitsize="32"/> > <reg name="pmpcfg1" bitsize="32"/> > <reg name="pmpcfg2" bitsize="32"/> > @@ -232,12 +234,11 @@ > <reg name="hedeleg" bitsize="32"/> > <reg name="hideleg" bitsize="32"/> > <reg name="hie" bitsize="32"/> > - <reg name="htvec" bitsize="32"/> > - <reg name="hscratch" bitsize="32"/> > - <reg name="hepc" bitsize="32"/> > - <reg name="hcause" bitsize="32"/> > - <reg name="hbadaddr" bitsize="32"/> > + <reg name="hcounteren" bitsize="32"/> > + <reg name="htval" bitsize="32"/> > <reg name="hip" bitsize="32"/> > + <reg name="htinst" bitsize="32"/> > + <reg name="hgatp" bitsize="32"/> > <reg name="mbase" bitsize="32"/> > <reg name="mbound" bitsize="32"/> > <reg name="mibase" bitsize="32"/> > diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml > index 6aa4bed9f50..90394562930 100644 > --- a/gdb-xml/riscv-64bit-csr.xml > +++ b/gdb-xml/riscv-64bit-csr.xml > @@ -110,6 +110,8 @@ > <reg name="mcause" bitsize="64"/> > <reg name="mtval" bitsize="64"/> > <reg name="mip" bitsize="64"/> > + <reg name="mtinst" bitsize="64"/> > + <reg name="mtval2" bitsize="64"/> > <reg name="pmpcfg0" bitsize="64"/> > <reg name="pmpcfg1" bitsize="64"/> > <reg name="pmpcfg2" bitsize="64"/> > @@ -232,12 +234,11 @@ > <reg name="hedeleg" bitsize="64"/> > <reg name="hideleg" bitsize="64"/> > <reg name="hie" bitsize="64"/> > - <reg name="htvec" bitsize="64"/> > - <reg name="hscratch" bitsize="64"/> > - <reg name="hepc" bitsize="64"/> > - <reg name="hcause" bitsize="64"/> > - <reg name="hbadaddr" bitsize="64"/> > + <reg name="hcounteren" bitsize="64"/> > + <reg name="htval" bitsize="64"/> > <reg name="hip" bitsize="64"/> > + <reg name="htinst" bitsize="64"/> > + <reg name="hgatp" bitsize="64"/> > <reg name="mbase" bitsize="64"/> > <reg name="mbound" bitsize="64"/> > <reg name="mibase" bitsize="64"/> > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index eba12a86f2e..f7c5212e274 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -418,13 +418,13 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > } > #if defined(TARGET_RISCV32) > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, > - 240, "riscv-32bit-csr.xml", 0); > + 241, "riscv-32bit-csr.xml", 0); > > gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, > 1, "riscv-32bit-virtual.xml", 0); > #elif defined(TARGET_RISCV64) > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, > - 240, "riscv-64bit-csr.xml", 0); > + 241, "riscv-64bit-csr.xml", 0); > > gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, > 1, "riscv-64bit-virtual.xml", 0); > -- > 2.17.1 > >
On Tue, Jan 26, 2021 at 7:54 AM Alistair Francis <alistair23@gmail.com> wrote: > On Tue, Jan 12, 2021 at 2:50 AM <frank.chang@sifive.com> wrote: > > > > From: Hsiangkai Wang <kai.wang@sifive.com> > > > > Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com> > > Acked-by: Richard Henderson <richard.henderson@linaro.org> > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > > This patch won't apply any more, we have removed the hardcoded GDB > register list. > > Alistair > Okay, I will update it in my next patchset. Thanks, Frank Chang > > > --- > > gdb-xml/riscv-32bit-csr.xml | 11 ++++++----- > > gdb-xml/riscv-64bit-csr.xml | 11 ++++++----- > > target/riscv/gdbstub.c | 4 ++-- > > 3 files changed, 14 insertions(+), 12 deletions(-) > > > > diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml > > index da1bf19e2f4..3d2031da7dc 100644 > > --- a/gdb-xml/riscv-32bit-csr.xml > > +++ b/gdb-xml/riscv-32bit-csr.xml > > @@ -110,6 +110,8 @@ > > <reg name="mcause" bitsize="32"/> > > <reg name="mtval" bitsize="32"/> > > <reg name="mip" bitsize="32"/> > > + <reg name="mtinst" bitsize="32"/> > > + <reg name="mtval2" bitsize="32"/> > > <reg name="pmpcfg0" bitsize="32"/> > > <reg name="pmpcfg1" bitsize="32"/> > > <reg name="pmpcfg2" bitsize="32"/> > > @@ -232,12 +234,11 @@ > > <reg name="hedeleg" bitsize="32"/> > > <reg name="hideleg" bitsize="32"/> > > <reg name="hie" bitsize="32"/> > > - <reg name="htvec" bitsize="32"/> > > - <reg name="hscratch" bitsize="32"/> > > - <reg name="hepc" bitsize="32"/> > > - <reg name="hcause" bitsize="32"/> > > - <reg name="hbadaddr" bitsize="32"/> > > + <reg name="hcounteren" bitsize="32"/> > > + <reg name="htval" bitsize="32"/> > > <reg name="hip" bitsize="32"/> > > + <reg name="htinst" bitsize="32"/> > > + <reg name="hgatp" bitsize="32"/> > > <reg name="mbase" bitsize="32"/> > > <reg name="mbound" bitsize="32"/> > > <reg name="mibase" bitsize="32"/> > > diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml > > index 6aa4bed9f50..90394562930 100644 > > --- a/gdb-xml/riscv-64bit-csr.xml > > +++ b/gdb-xml/riscv-64bit-csr.xml > > @@ -110,6 +110,8 @@ > > <reg name="mcause" bitsize="64"/> > > <reg name="mtval" bitsize="64"/> > > <reg name="mip" bitsize="64"/> > > + <reg name="mtinst" bitsize="64"/> > > + <reg name="mtval2" bitsize="64"/> > > <reg name="pmpcfg0" bitsize="64"/> > > <reg name="pmpcfg1" bitsize="64"/> > > <reg name="pmpcfg2" bitsize="64"/> > > @@ -232,12 +234,11 @@ > > <reg name="hedeleg" bitsize="64"/> > > <reg name="hideleg" bitsize="64"/> > > <reg name="hie" bitsize="64"/> > > - <reg name="htvec" bitsize="64"/> > > - <reg name="hscratch" bitsize="64"/> > > - <reg name="hepc" bitsize="64"/> > > - <reg name="hcause" bitsize="64"/> > > - <reg name="hbadaddr" bitsize="64"/> > > + <reg name="hcounteren" bitsize="64"/> > > + <reg name="htval" bitsize="64"/> > > <reg name="hip" bitsize="64"/> > > + <reg name="htinst" bitsize="64"/> > > + <reg name="hgatp" bitsize="64"/> > > <reg name="mbase" bitsize="64"/> > > <reg name="mbound" bitsize="64"/> > > <reg name="mibase" bitsize="64"/> > > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > > index eba12a86f2e..f7c5212e274 100644 > > --- a/target/riscv/gdbstub.c > > +++ b/target/riscv/gdbstub.c > > @@ -418,13 +418,13 @@ void > riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > > } > > #if defined(TARGET_RISCV32) > > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, > > - 240, "riscv-32bit-csr.xml", 0); > > + 241, "riscv-32bit-csr.xml", 0); > > > > gdb_register_coprocessor(cs, riscv_gdb_get_virtual, > riscv_gdb_set_virtual, > > 1, "riscv-32bit-virtual.xml", 0); > > #elif defined(TARGET_RISCV64) > > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, > > - 240, "riscv-64bit-csr.xml", 0); > > + 241, "riscv-64bit-csr.xml", 0); > > > > gdb_register_coprocessor(cs, riscv_gdb_get_virtual, > riscv_gdb_set_virtual, > > 1, "riscv-64bit-virtual.xml", 0); > > -- > > 2.17.1 > > > > >
diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml index da1bf19e2f4..3d2031da7dc 100644 --- a/gdb-xml/riscv-32bit-csr.xml +++ b/gdb-xml/riscv-32bit-csr.xml @@ -110,6 +110,8 @@ <reg name="mcause" bitsize="32"/> <reg name="mtval" bitsize="32"/> <reg name="mip" bitsize="32"/> + <reg name="mtinst" bitsize="32"/> + <reg name="mtval2" bitsize="32"/> <reg name="pmpcfg0" bitsize="32"/> <reg name="pmpcfg1" bitsize="32"/> <reg name="pmpcfg2" bitsize="32"/> @@ -232,12 +234,11 @@ <reg name="hedeleg" bitsize="32"/> <reg name="hideleg" bitsize="32"/> <reg name="hie" bitsize="32"/> - <reg name="htvec" bitsize="32"/> - <reg name="hscratch" bitsize="32"/> - <reg name="hepc" bitsize="32"/> - <reg name="hcause" bitsize="32"/> - <reg name="hbadaddr" bitsize="32"/> + <reg name="hcounteren" bitsize="32"/> + <reg name="htval" bitsize="32"/> <reg name="hip" bitsize="32"/> + <reg name="htinst" bitsize="32"/> + <reg name="hgatp" bitsize="32"/> <reg name="mbase" bitsize="32"/> <reg name="mbound" bitsize="32"/> <reg name="mibase" bitsize="32"/> diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml index 6aa4bed9f50..90394562930 100644 --- a/gdb-xml/riscv-64bit-csr.xml +++ b/gdb-xml/riscv-64bit-csr.xml @@ -110,6 +110,8 @@ <reg name="mcause" bitsize="64"/> <reg name="mtval" bitsize="64"/> <reg name="mip" bitsize="64"/> + <reg name="mtinst" bitsize="64"/> + <reg name="mtval2" bitsize="64"/> <reg name="pmpcfg0" bitsize="64"/> <reg name="pmpcfg1" bitsize="64"/> <reg name="pmpcfg2" bitsize="64"/> @@ -232,12 +234,11 @@ <reg name="hedeleg" bitsize="64"/> <reg name="hideleg" bitsize="64"/> <reg name="hie" bitsize="64"/> - <reg name="htvec" bitsize="64"/> - <reg name="hscratch" bitsize="64"/> - <reg name="hepc" bitsize="64"/> - <reg name="hcause" bitsize="64"/> - <reg name="hbadaddr" bitsize="64"/> + <reg name="hcounteren" bitsize="64"/> + <reg name="htval" bitsize="64"/> <reg name="hip" bitsize="64"/> + <reg name="htinst" bitsize="64"/> + <reg name="hgatp" bitsize="64"/> <reg name="mbase" bitsize="64"/> <reg name="mbound" bitsize="64"/> <reg name="mibase" bitsize="64"/> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index eba12a86f2e..f7c5212e274 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -418,13 +418,13 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } #if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 240, "riscv-32bit-csr.xml", 0); + 241, "riscv-32bit-csr.xml", 0); gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-32bit-virtual.xml", 0); #elif defined(TARGET_RISCV64) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 240, "riscv-64bit-csr.xml", 0); + 241, "riscv-64bit-csr.xml", 0); gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-64bit-virtual.xml", 0);