| Message ID | 20210112093950.17530-5-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support vector extension v1.0 | expand |
On Tue, Jan 12, 2021 at 1:51 AM <frank.chang@sifive.com> wrote: > > From: LIU Zhiwei <zhiwei_liu@c-sky.com> > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_bits.h | 1 + > target/riscv/csr.c | 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 82c48b7b9be..8edf81692e6 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -414,6 +414,7 @@ > #define SSTATUS_UPIE 0x00000010 > #define SSTATUS_SPIE 0x00000020 > #define SSTATUS_SPP 0x00000100 > +#define SSTATUS_VS 0x00000600 > #define SSTATUS_FS 0x00006000 > #define SSTATUS_XS 0x00018000 > #define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 50862df9e82..a70a78386da 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -448,7 +448,7 @@ static const target_ulong delegable_excps = > (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); > static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | > SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | > - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; > + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD | SSTATUS_VS; > static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; > static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > static const target_ulong vsip_writable_mask = MIP_VSSIP; > -- > 2.17.1 > >
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 82c48b7b9be..8edf81692e6 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -414,6 +414,7 @@ #define SSTATUS_UPIE 0x00000010 #define SSTATUS_SPIE 0x00000020 #define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 #define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 50862df9e82..a70a78386da 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -448,7 +448,7 @@ static const target_ulong delegable_excps = (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD | SSTATUS_VS; static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP;