Message ID | 20210617174323.2900831-2-f4bug@amsat.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | target/mips: Various fixes & cleanups | expand |
On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote: > On real hardware an invalid instruction doesn't halt the world, > but usually triggers a RESERVED INSTRUCTION exception. > TCG guest code shouldn't abort QEMU anyway. > > Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org> > --- > target/mips/tcg/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 0954ce0dbc3..b92a473f870 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -12151,8 +12151,8 @@ static void gen_branch(DisasContext *ctx, int insn_bytes) tcg_gen_lookup_and_goto_ptr(); break; default: - fprintf(stderr, "unknown branch 0x%x\n", proc_hflags); - abort(); + LOG_DISAS("unknown branch 0x%x\n", proc_hflags); + gen_reserved_instruction(ctx); } } }
On real hardware an invalid instruction doesn't halt the world, but usually triggers a RESERVED INSTRUCTION exception. TCG guest code shouldn't abort QEMU anyway. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)