[v10,42/77] target/riscv: rvv-1.0: single-width bit shift instructions

From: Frank Chang <frank.chang@sifive.com>

From: frank.chang@sifive.com
To: qemu-devel@nongnu.org
Subject: [PATCH v10 42/77] target/riscv: rvv-1.0: single-width bit shift
 instructions
Date: Mon, 29 Nov 2021 11:03:02 +0800
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Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
 Bin Meng <bin.meng@windriver.com>,
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 Palmer Dabbelt <palmer@dabbelt.com>, LIU Zhiwei <zhiwei_liu@c-sky.com>
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Message ID	20211129030340.429689-43-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v10 42/77] target/riscv: rvv-1.0: single-width bit shift instructions Date: Mon, 29 Nov 2021 11:03:02 +0800 Message-Id: <20211129030340.429689-43-frank.chang@sifive.com> In-Reply-To: <20211129030340.429689-1-frank.chang@sifive.com> References: <20211129030340.429689-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	support vector extension v1.0 \| expand [v10,00/77] support vector extension v1.0 [v10,01/77] target/riscv: drop vector 0.7.1 and add 1.0 support [v10,02/77] target/riscv: Use FIELD_EX32() to extract wd field [v10,03/77] target/riscv: rvv-1.0: add mstatus VS field [v10,04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty [v10,05/77] target/riscv: rvv-1.0: add sstatus VS field [v10,06/77] target/riscv: rvv-1.0: introduce writable misa.v field [v10,07/77] target/riscv: rvv-1.0: add translation-time vector context status [v10,08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers [v10,09/77] target/riscv: rvv-1.0: add vcsr register [v10,10/77] target/riscv: rvv-1.0: add vlenb register [v10,11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers [v10,12/77] target/riscv: rvv-1.0: remove MLEN calculations [v10,13/77] target/riscv: rvv-1.0: add fractional LMUL [v10,14/77] target/riscv: rvv-1.0: add VMA and VTA [v10,15/77] target/riscv: rvv-1.0: update check functions [v10,16/77] target/riscv: introduce more imm value modes in translator functions [v10,17/77] target/riscv: rvv:1.0: add translation-time nan-box helper function [v10,18/77] target/riscv: rvv-1.0: remove amo operations instructions [v10,19/77] target/riscv: rvv-1.0: configure instructions [v10,20/77] target/riscv: rvv-1.0: stride load and store instructions [v10,21/77] target/riscv: rvv-1.0: index load and store instructions [v10,22/77] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns [v10,23/77] target/riscv: rvv-1.0: fault-only-first unit stride load [v10,24/77] target/riscv: rvv-1.0: load/store whole register instructions [v10,25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns [v10,26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation [v10,27/77] target/riscv: rvv-1.0: floating-point square-root instruction [v10,28/77] target/riscv: rvv-1.0: floating-point classify instructions [v10,29/77] target/riscv: rvv-1.0: count population in mask instruction [v10,30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction [v10,31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions [v10,32/77] target/riscv: rvv-1.0: iota instruction [v10,33/77] target/riscv: rvv-1.0: element index instruction [v10,34/77] target/riscv: rvv-1.0: allow load element with sign-extended [v10,35/77] target/riscv: rvv-1.0: register gather instructions [v10,36/77] target/riscv: rvv-1.0: integer scalar move instructions [v10,37/77] target/riscv: rvv-1.0: floating-point move instruction [v10,38/77] target/riscv: rvv-1.0: floating-point scalar move instructions [v10,39/77] target/riscv: rvv-1.0: whole register move instructions [v10,40/77] target/riscv: rvv-1.0: integer extension instructions [v10,41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions [v10,42/77] target/riscv: rvv-1.0: single-width bit shift instructions [v10,43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow [v10,44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions [v10,45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions [v10,46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions [v10,47/77] target/riscv: rvv-1.0: integer comparison instructions [v10,48/77] target/riscv: rvv-1.0: floating-point compare instructions [v10,49/77] target/riscv: rvv-1.0: mask-register logical instructions [v10,50/77] target/riscv: rvv-1.0: slide instructions [v10,51/77] target/riscv: rvv-1.0: floating-point slide instructions [v10,52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions [v10,53/77] target/riscv: rvv-1.0: single-width floating-point reduction [v10,54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions [v10,55/77] target/riscv: rvv-1.0: single-width scaling shift instructions [v10,56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add [v10,57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf [v10,58/77] target/riscv: rvv-1.0: remove integer extract instruction [v10,59/77] target/riscv: rvv-1.0: floating-point min/max instructions [v10,60/77] target/riscv: introduce floating-point rounding mode enum [v10,61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions [v10,62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert [v10,63/77] target/riscv: add "set round to odd" rounding mode helper function [v10,64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert [v10,65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits [v10,66/77] target/riscv: rvv-1.0: implement vstart CSR [v10,67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid [v10,68/77] target/riscv: gdb: support vector registers for rv64 & rv32 [v10,69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction [v10,70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction [v10,71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 [v10,72/77] target/riscv: rvv-1.0: add vsetivli instruction [v10,73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() [v10,74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns [v10,75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm [v10,76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment [v10,77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions

[v10,42/77] target/riscv: rvv-1.0: single-width bit shift instructions

Commit Message

Patch