| Message ID | 20220215214148.1848266-9-farosas@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/ppc: SPR registration cleanups | expand |
On Tue, Feb 15, 2022 at 06:41:29PM -0300, Fabiano Rosas wrote: > We're considering these two to be in different CPU families (6xx and > 7xx), so keep their SPR registration separate. > > The code was copied into register_G2_sprs and the common function was > renamed to apply only to the 755. > > Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > target/ppc/cpu_init.c | 25 ++++++++++++++++++++----- > 1 file changed, 20 insertions(+), 5 deletions(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 29f25e093f..6a367f2bbc 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -466,8 +466,7 @@ static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways > #endif > } > > -/* SPR common to MPC755 and G2 */ > -static void register_G2_755_sprs(CPUPPCState *env) > +static void register_755_sprs(CPUPPCState *env) > { > /* SGPRs */ > spr_register(env, SPR_SPRG4, "SPRG4", > @@ -783,6 +782,23 @@ static void register_G2_sprs(CPUPPCState *env) > &spr_read_generic, &spr_write_generic, > 0x00000000); > > + /* SGPRs */ > + spr_register(env, SPR_SPRG4, "SPRG4", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register(env, SPR_SPRG5, "SPRG5", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register(env, SPR_SPRG6, "SPRG6", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register(env, SPR_SPRG7, "SPRG7", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > } > > static void register_74xx_sprs(CPUPPCState *env) > @@ -2852,7 +2868,6 @@ static void init_proc_G2(CPUPPCState *env) > { > register_ne_601_sprs(env); > register_sdr1_sprs(env); > - register_G2_755_sprs(env); > register_G2_sprs(env); > > /* Memory management */ > @@ -4474,7 +4489,7 @@ static void init_proc_745(CPUPPCState *env) > register_ne_601_sprs(env); > register_sdr1_sprs(env); > register_7xx_sprs(env); > - register_G2_755_sprs(env); > + register_755_sprs(env); > /* Thermal management */ > register_thrm_sprs(env); > /* Hardware implementation registers */ > @@ -4547,7 +4562,7 @@ static void init_proc_755(CPUPPCState *env) > register_ne_601_sprs(env); > register_sdr1_sprs(env); > register_7xx_sprs(env); > - register_G2_755_sprs(env); > + register_755_sprs(env); > /* L2 cache control */ > spr_register(env, SPR_L2CR, "L2CR", > SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 29f25e093f..6a367f2bbc 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -466,8 +466,7 @@ static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways #endif } -/* SPR common to MPC755 and G2 */ -static void register_G2_755_sprs(CPUPPCState *env) +static void register_755_sprs(CPUPPCState *env) { /* SGPRs */ spr_register(env, SPR_SPRG4, "SPRG4", @@ -783,6 +782,23 @@ static void register_G2_sprs(CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x00000000); + /* SGPRs */ + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); } static void register_74xx_sprs(CPUPPCState *env) @@ -2852,7 +2868,6 @@ static void init_proc_G2(CPUPPCState *env) { register_ne_601_sprs(env); register_sdr1_sprs(env); - register_G2_755_sprs(env); register_G2_sprs(env); /* Memory management */ @@ -4474,7 +4489,7 @@ static void init_proc_745(CPUPPCState *env) register_ne_601_sprs(env); register_sdr1_sprs(env); register_7xx_sprs(env); - register_G2_755_sprs(env); + register_755_sprs(env); /* Thermal management */ register_thrm_sprs(env); /* Hardware implementation registers */ @@ -4547,7 +4562,7 @@ static void init_proc_755(CPUPPCState *env) register_ne_601_sprs(env); register_sdr1_sprs(env); register_7xx_sprs(env); - register_G2_755_sprs(env); + register_755_sprs(env); /* L2 cache control */ spr_register(env, SPR_L2CR, "L2CR", SPR_NOACCESS, SPR_NOACCESS,
We're considering these two to be in different CPU families (6xx and 7xx), so keep their SPR registration separate. The code was copied into register_G2_sprs and the common function was renamed to apply only to the 755. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> --- target/ppc/cpu_init.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-)