Message ID | 20220901162613.6939-28-shentey@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Consolidate PIIX south bridges | expand |
On 1/9/22 18:25, Bernhard Beschow wrote: > PIIX3 initializes the PIRQx route control registers to the default > values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4) > April 1997 manual. PIIX4, however, initializes the routes according to > the Malta™ User’s Manual, ch 6.6, which are IRQs 10 and 11. In order to > allow the reset methods to be consolidated, allow board code to specify > the routes. > > Signed-off-by: Bernhard Beschow <shentey@gmail.com> > --- > hw/isa/piix4.c | 14 ++++++++++---- > hw/mips/malta.c | 4 ++++ > 2 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c > index ed9eca715f..763c98b565 100644 > --- a/hw/isa/piix4.c > +++ b/hw/isa/piix4.c > @@ -57,6 +57,8 @@ struct PIIX4State { > MemoryRegion rcr_mem; > uint8_t rcr; > > + uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; > + > bool has_acpi; > bool has_usb; > bool smm_enabled; > @@ -122,10 +124,10 @@ static void piix4_isa_reset(DeviceState *dev) > pci_conf[0x4c] = 0x4d; > pci_conf[0x4e] = 0x03; > pci_conf[0x4f] = 0x00; > - pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 > - pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 > - pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 > - pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 > + pci_conf[PIIX_PIRQCA] = d->pci_irq_reset_mappings[0]; > + pci_conf[PIIX_PIRQCB] = d->pci_irq_reset_mappings[1]; > + pci_conf[PIIX_PIRQCC] = d->pci_irq_reset_mappings[2]; > + pci_conf[PIIX_PIRQCD] = d->pci_irq_reset_mappings[3]; > pci_conf[0x69] = 0x02; > pci_conf[0x70] = 0x80; > pci_conf[0x76] = 0x0c; > @@ -299,6 +301,10 @@ static void piix4_init(Object *obj) > > static Property piix4_props[] = { > DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), > + DEFINE_PROP_UINT8("pirqa", PIIX4State, pci_irq_reset_mappings[0], 0x80), > + DEFINE_PROP_UINT8("pirqb", PIIX4State, pci_irq_reset_mappings[1], 0x80), > + DEFINE_PROP_UINT8("pirqc", PIIX4State, pci_irq_reset_mappings[2], 0x80), > + DEFINE_PROP_UINT8("pirqd", PIIX4State, pci_irq_reset_mappings[3], 0x80), > DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), > DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), > DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), > diff --git a/hw/mips/malta.c b/hw/mips/malta.c > index 6339b0d66c..44b6b14f3d 100644 > --- a/hw/mips/malta.c > +++ b/hw/mips/malta.c > @@ -1403,6 +1403,10 @@ void mips_malta_init(MachineState *machine) > piix4 = pci_new_multifunction(PCI_DEVFN(10, 0), true, > TYPE_PIIX4_PCI_DEVICE); > qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); > + qdev_prop_set_uint8(DEVICE(piix4), "pirqa", 10); > + qdev_prop_set_uint8(DEVICE(piix4), "pirqb", 10); > + qdev_prop_set_uint8(DEVICE(piix4), "pirqc", 11); > + qdev_prop_set_uint8(DEVICE(piix4), "pirqd", 11); > pci_realize_and_unref(piix4, pci_bus, &error_fatal); > isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); > Nice! Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index ed9eca715f..763c98b565 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -57,6 +57,8 @@ struct PIIX4State { MemoryRegion rcr_mem; uint8_t rcr; + uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; + bool has_acpi; bool has_usb; bool smm_enabled; @@ -122,10 +124,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] = 0x4d; pci_conf[0x4e] = 0x03; pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 + pci_conf[PIIX_PIRQCA] = d->pci_irq_reset_mappings[0]; + pci_conf[PIIX_PIRQCB] = d->pci_irq_reset_mappings[1]; + pci_conf[PIIX_PIRQCC] = d->pci_irq_reset_mappings[2]; + pci_conf[PIIX_PIRQCD] = d->pci_irq_reset_mappings[3]; pci_conf[0x69] = 0x02; pci_conf[0x70] = 0x80; pci_conf[0x76] = 0x0c; @@ -299,6 +301,10 @@ static void piix4_init(Object *obj) static Property piix4_props[] = { DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), + DEFINE_PROP_UINT8("pirqa", PIIX4State, pci_irq_reset_mappings[0], 0x80), + DEFINE_PROP_UINT8("pirqb", PIIX4State, pci_irq_reset_mappings[1], 0x80), + DEFINE_PROP_UINT8("pirqc", PIIX4State, pci_irq_reset_mappings[2], 0x80), + DEFINE_PROP_UINT8("pirqd", PIIX4State, pci_irq_reset_mappings[3], 0x80), DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 6339b0d66c..44b6b14f3d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1403,6 +1403,10 @@ void mips_malta_init(MachineState *machine) piix4 = pci_new_multifunction(PCI_DEVFN(10, 0), true, TYPE_PIIX4_PCI_DEVICE); qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); + qdev_prop_set_uint8(DEVICE(piix4), "pirqa", 10); + qdev_prop_set_uint8(DEVICE(piix4), "pirqb", 10); + qdev_prop_set_uint8(DEVICE(piix4), "pirqc", 11); + qdev_prop_set_uint8(DEVICE(piix4), "pirqd", 11); pci_realize_and_unref(piix4, pci_bus, &error_fatal); isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
PIIX3 initializes the PIRQx route control registers to the default values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4) April 1997 manual. PIIX4, however, initializes the routes according to the Malta™ User’s Manual, ch 6.6, which are IRQs 10 and 11. In order to allow the reset methods to be consolidated, allow board code to specify the routes. Signed-off-by: Bernhard Beschow <shentey@gmail.com> --- hw/isa/piix4.c | 14 ++++++++++---- hw/mips/malta.c | 4 ++++ 2 files changed, 14 insertions(+), 4 deletions(-)