@@ -43,9 +43,8 @@
struct PIIX4State {
PCIDevice dev;
- qemu_irq cpu_intr;
- qemu_irq *isa;
+ ISAPICState pic;
RTCState rtc;
PCIIDEState ide;
UHCIState uhci;
@@ -83,7 +82,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
pic_level |= pci_bus_get_irq_level(bus, i);
}
}
- qemu_set_irq(s->isa[pic_irq], pic_level);
+ qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level);
}
}
@@ -175,12 +174,6 @@ static const VMStateDescription vmstate_piix4 = {
}
};
-static void piix4_request_i8259_irq(void *opaque, int irq, int level)
-{
- PIIX4State *s = opaque;
- qemu_set_irq(s->cpu_intr, level);
-}
-
static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int len)
{
@@ -216,7 +209,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
PIIX4State *s = PIIX4_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
- qemu_irq *i8259_out_irq;
isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
pci_address_space_io(dev), errp);
@@ -224,20 +216,18 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
- qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
- "intr", 1);
-
memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
"reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev),
PIIX_RCR_IOPORT, &s->rcr_mem, 1);
/* initialize i8259 pic */
- i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
- s->isa = i8259_init(isa_bus, *i8259_out_irq);
+ if (!qdev_realize(DEVICE(&s->pic), BUS(isa_bus), errp)) {
+ return;
+ }
/* initialize ISA irqs */
- isa_bus_irqs(isa_bus, s->isa);
+ isa_bus_irqs(isa_bus, s->pic.in_irqs);
/* initialize pit */
i8254_pit_init(isa_bus, 0x40, 0, NULL);
@@ -250,7 +240,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
return;
}
- s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
+ s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq);
/* IDE */
qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1);
@@ -277,7 +267,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
return;
}
- qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]);
+ qdev_connect_gpio_out(DEVICE(&s->pm), 0,
+ qdev_get_gpio_in(DEVICE(&s->pic), 9));
}
pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
@@ -287,6 +278,7 @@ static void piix4_init(Object *obj)
{
PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+ object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &s->ide, "piix4-ide");
}
@@ -28,6 +28,7 @@
#include "qemu/datadir.h"
#include "hw/clock.h"
#include "hw/southbridge/piix.h"
+#include "hw/intc/i8259.h"
#include "hw/isa/superio.h"
#include "hw/char/serial.h"
#include "net/net.h"
@@ -1232,10 +1233,11 @@ void mips_malta_init(MachineState *machine)
PCIBus *pci_bus;
ISABus *isa_bus;
qemu_irq cbus_irq, i8259_irq;
+ qemu_irq *i8259;
I2CBus *smbus;
DriveInfo *dinfo;
int fl_idx = 0;
- int be;
+ int be, i;
MaltaState *s;
PCIDevice *piix4;
DeviceState *dev;
@@ -1414,7 +1416,12 @@ void mips_malta_init(MachineState *machine)
pci_ide_create_devs(PCI_DEVICE(dev));
/* Interrupt controller */
- qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq);
+ dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pic"));
+ i8259 = i8259_init(isa_bus, i8259_irq);
+ for (i = 0; i < ISA_NUM_IRQS; i++) {
+ qdev_connect_gpio_out(dev, i, i8259[i]);
+ }
+ g_free(i8259);
/* generate SPD EEPROM data */
dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm"));
Aligns the code with PIIX3 such that PIIXState can be used in PIIX4, too. Furthermore, using the isa-pic device in PIIX4 could allow the Malta board to gain KVM accelleration capabilities. Signed-off-by: Bernhard Beschow <shentey@gmail.com> --- hw/isa/piix4.c | 28 ++++++++++------------------ hw/mips/malta.c | 11 +++++++++-- 2 files changed, 19 insertions(+), 20 deletions(-)