| Message ID | 20230325105429.1142530-19-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: MSTATUS_SUM + cleanups | expand |
On Sat, Mar 25, 2023 at 10:29 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > Move the check from the top of get_physical_address to > the two callers, where passing mmu_idx makes no sense. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 10 ++-------- > 1 file changed, 2 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 0017ecbf37..833ea6d3fa 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -791,12 +791,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, > use_background = true; > } > > - if (first_stage == false) { > - /* We are in stage 2 translation, this is similar to stage 1. */ > - /* Stage 2 is always taken as U-mode */ > - mode = PRV_U; > - } > - > if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { > *physical = addr; > *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; > @@ -902,7 +896,7 @@ restart: > /* Do the second stage translation on the base PTE address. */ > int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, > base, NULL, MMU_DATA_LOAD, > - mmu_idx, false, true, > + MMUIdx_U, false, true, > is_debug); > > if (vbase_ret != TRANSLATE_SUCCESS) { > @@ -1274,7 +1268,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > im_address = pa; > > ret = get_physical_address(env, &pa, &prot2, im_address, NULL, > - access_type, mmu_idx, false, true, > + access_type, MMUIdx_U, false, true, > false); > > qemu_log_mask(CPU_LOG_MMU, > -- > 2.34.1 > >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0017ecbf37..833ea6d3fa 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -791,12 +791,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, use_background = true; } - if (first_stage == false) { - /* We are in stage 2 translation, this is similar to stage 1. */ - /* Stage 2 is always taken as U-mode */ - mode = PRV_U; - } - if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { *physical = addr; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -902,7 +896,7 @@ restart: /* Do the second stage translation on the base PTE address. */ int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, base, NULL, MMU_DATA_LOAD, - mmu_idx, false, true, + MMUIdx_U, false, true, is_debug); if (vbase_ret != TRANSLATE_SUCCESS) { @@ -1274,7 +1268,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, im_address = pa; ret = get_physical_address(env, &pa, &prot2, im_address, NULL, - access_type, mmu_idx, false, true, + access_type, MMUIdx_U, false, true, false); qemu_log_mask(CPU_LOG_MMU,
Move the check from the top of get_physical_address to the two callers, where passing mmu_idx makes no sense. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-)