| Message ID | 20230325105429.1142530-26-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: MSTATUS_SUM + cleanups | expand |
On Sat, Mar 25, 2023 at 10:56 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > Implement this by adjusting prot, which reduces the set of > checks required. This prevents exec to be set for U pages > in MMUIdx_S_SUM. While it had been technically incorrect, > it did not manifest as a bug, because we will never attempt > to execute from MMUIdx_S_SUM. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 725ca45106..7336d1273b 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -800,7 +800,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, > *ret_prot = 0; > > hwaddr base; > - int levels, ptidxbits, ptesize, vm, sum, widened; > + int levels, ptidxbits, ptesize, vm, widened; > > if (first_stage == true) { > if (use_background) { > @@ -831,7 +831,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, > } > widened = 2; > } > - sum = mmuidx_sum(mmu_idx); > + > switch (vm) { > case VM_1_10_SV32: > levels = 2; ptidxbits = 10; ptesize = 4; break; > @@ -999,15 +999,15 @@ restart: > prot |= PAGE_EXEC; > } > > - if ((pte & PTE_U) && > - ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) { > - /* > - * User PTE flags when not U mode and mstatus.SUM is not set, > - * or the access type is an instruction fetch. > - */ > - return TRANSLATE_FAIL; > - } > - if (!(pte & PTE_U) && (mode != PRV_S)) { > + if (pte & PTE_U) { > + if (mode != PRV_U) { > + if (!mmuidx_sum(mmu_idx)) { > + return TRANSLATE_FAIL; > + } > + /* SUM allows only read+write, not execute. */ > + prot &= PAGE_READ | PAGE_WRITE; > + } > + } else if (mode != PRV_S) { > /* Supervisor PTE flags when not S mode */ > return TRANSLATE_FAIL; > } > -- > 2.34.1 > >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 725ca45106..7336d1273b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -800,7 +800,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, *ret_prot = 0; hwaddr base; - int levels, ptidxbits, ptesize, vm, sum, widened; + int levels, ptidxbits, ptesize, vm, widened; if (first_stage == true) { if (use_background) { @@ -831,7 +831,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } widened = 2; } - sum = mmuidx_sum(mmu_idx); + switch (vm) { case VM_1_10_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break; @@ -999,15 +999,15 @@ restart: prot |= PAGE_EXEC; } - if ((pte & PTE_U) && - ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) { - /* - * User PTE flags when not U mode and mstatus.SUM is not set, - * or the access type is an instruction fetch. - */ - return TRANSLATE_FAIL; - } - if (!(pte & PTE_U) && (mode != PRV_S)) { + if (pte & PTE_U) { + if (mode != PRV_U) { + if (!mmuidx_sum(mmu_idx)) { + return TRANSLATE_FAIL; + } + /* SUM allows only read+write, not execute. */ + prot &= PAGE_READ | PAGE_WRITE; + } + } else if (mode != PRV_S) { /* Supervisor PTE flags when not S mode */ return TRANSLATE_FAIL; }
Implement this by adjusting prot, which reduces the set of checks required. This prevents exec to be set for U pages in MMUIdx_S_SUM. While it had been technically incorrect, it did not manifest as a bug, because we will never attempt to execute from MMUIdx_S_SUM. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-)