diff mbox series

[PULL,21/49] target/riscv: pmp: Ignore writes when RW=01

Message ID	20231107022946.1055027-22-alistair.francis@wdc.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Mayuresh Chitale <mchitale@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 21/49] target/riscv: pmp: Ignore writes when RW=01 Date: Tue, 7 Nov 2023 12:29:17 +1000 Message-ID: <20231107022946.1055027-22-alistair.francis@wdc.com> In-Reply-To: <20231107022946.1055027-1-alistair.francis@wdc.com> References: <20231107022946.1055027-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei \| expand [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei [PULL,02/49] target/riscv: rename ext_icsr to ext_zicsr [PULL,03/49] target/riscv: rename ext_icbom to ext_zicbom [PULL,04/49] target/riscv: rename ext_icboz to ext_zicboz [PULL,05/49] target/riscv: Without H-mode mask all HS mode inturrupts in mie. [PULL,06/49] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. [PULL,07/49] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled [PULL,08/49] target/riscv: Split interrupt logic from riscv_cpu_update_mip. [PULL,09/49] target/riscv: Add M-mode virtual interrupt and IRQ filtering support. [PULL,10/49] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. [PULL,11/49] linux-user/riscv: change default cpu to 'max' [PULL,12/49] docs/system/riscv: update 'virt' machine core limit [PULL,13/49] target/riscv/kvm/kvm-cpu.c: add missing property getters() [PULL,14/49] qapi,risc-v: add query-cpu-model-expansion [PULL,15/49] target/riscv/tcg: add tcg_cpu_finalize_features() [PULL,16/49] target/riscv: handle custom props in qmp_query_cpu_model_expansion [PULL,17/49] target/riscv: add riscv_cpu_accelerator_compatible() [PULL,18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion [PULL,19/49] Add epmp to extensions list and rename it to smepmp [PULL,20/49] target/riscv: pmp: Clear pmp/smepmp bits on reset [PULL,21/49] target/riscv: pmp: Ignore writes when RW=01 [PULL,22/49] target/riscv: add zicntr extension flag for TCG [PULL,23/49] target/riscv/kvm: add zicntr reg [PULL,24/49] target/riscv: add zihpm extension flag for TCG [PULL,25/49] target/riscv/kvm: add zihpm reg [PULL,26/49] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot [PULL,27/49] target/riscv: correct csr_ops[CSR_MSECCFG] [PULL,28/49] MAINTAINERS: update mail address for Weiwei Li [PULL,29/49] target/riscv: Add cfg property for Zvkt extension [PULL,30/49] target/riscv: Expose Zvkt extension property [PULL,31/49] target/riscv: Add cfg property for Zvkb extension [PULL,32/49] target/riscv: Replace Zvbb checking by Zvkb [PULL,33/49] target/riscv: Expose Zvkb extension property [PULL,34/49] target/riscv: Add cfg properties for Zvkn[c\|g] extensions [PULL,35/49] target/riscv: Expose Zvkn[c\|g] extnesion properties [PULL,36/49] target/riscv: Add cfg properties for Zvks[c\|g] extensions [PULL,37/49] target/riscv: Expose Zvks[c\|g] extnesion properties [PULL,38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions [PULL,39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format [PULL,40/49] disas/riscv: Add rv_codec_vror_vi for vror.vi [PULL,41/49] disas/riscv: Add support for vector crypto extensions [PULL,42/49] disas/riscv: Replace TABs with space [PULL,43/49] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled [PULL,44/49] target/riscv: cpu: Set the OpenTitan priv to 1.12.0 [PULL,45/49] target/riscv: Propagate error from PMU setup [PULL,46/49] target/riscv: Don't assume PMU counters are continuous [PULL,47/49] target/riscv: Use existing PMU counter mask in FDT generation [PULL,48/49] target/riscv: Add "pmu-mask" property to replace "pmu-num" [PULL,49/49] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

Commit Message

Alistair Francis Nov. 7, 2023, 2:29 a.m. UTC

From: Mayuresh Chitale <mchitale@ventanamicro.com>

As per the Priv spec: "The R, W, and X fields form a collective WARL
field for which the combinations with R=0 and W=1 are reserved."
However currently such writes are not ignored as ought to be. The
combinations with RW=01 are allowed only when the Smepmp extension
is enabled and mseccfg.MML is set.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231019065705.1431868-1-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 5 +++++
 1 file changed, 5 insertions(+)

diff mbox series

Patch

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 4dfaa28fce..162e88a90a 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -123,6 +123,11 @@  static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
         if (locked) {
             qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
         } else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) {
+            /* If !mseccfg.MML then ignore writes with encoding RW=01 */
+            if ((val & PMP_WRITE) && !(val & PMP_READ) &&
+                !MSECCFG_MML_ISSET(env)) {
+                val &= ~(PMP_WRITE | PMP_READ);
+            }
             env->pmp_state.pmp[pmp_index].cfg_reg = val;
             pmp_update_rule_addr(env, pmp_index);
             return true;