Message ID | 20231107022946.1055027-45-alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Series |
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
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diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d73e1da2a2..70c0a78c6c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -606,7 +606,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - env->priv_ver = PRIV_VERSION_1_11_0; + env->priv_ver = PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif