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[PULL,05/49] target/riscv: Without H-mode mask all HS mode inturrupts in mie.

Message ID 20231107022946.1055027-6-alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei | expand

Commit Message

Alistair Francis Nov. 7, 2023, 2:29 a.m. UTC 
From: Rajnesh Kanwal <rkanwal@rivosinc.com>

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-2-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 30cc21e979..4847b47a98 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1525,7 +1525,7 @@  static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
     env->mie = (env->mie & ~mask) | (new_val & mask);
 
     if (!riscv_has_ext(env, RVH)) {
-        env->mie &= ~((uint64_t)MIP_SGEIP);
+        env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS);
     }
 
     return RISCV_EXCP_NONE;