Message ID | 20230113052914.3845596-4-Penny.Zheng@arm.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | xen/arm: Add Armv8-R64 MPU support to Xen - Part#1 | expand |
Hi, On 13/01/2023 05:28, Penny Zheng wrote: > From: Wei Chen <wei.chen@arm.com> > > From Arm ARM Supplement of Armv8-R AArch64 (DDI 0600A) [1], > section D1.6.2 TLB maintenance instructions, we know that > Armv8-R AArch64 permits an implementation to cache stage 1 > VMSAv8-64 and stage 2 PMSAv8-64 attributes as a common entry > for the Secure EL1&0 translation regime. But for Xen itself, > it's running with stage 1 PMSAv8-64 on Armv8-R AArch64. The > EL2 MPU updates for stage 1 PMSAv8-64 will not be cached in > TLB entries. So we don't need any TLB invalidation for Xen > itself in EL2. So I understand the theory here. But I would expect that none of the common code will call any of those helpers. Therefore the #ifdef should be unnecessary. Can you clarify if my understanding is correct? Cheers,
Hi Julien, > -----Original Message----- > From: Julien Grall <julien@xen.org> > Sent: 2023年1月18日 7:17 > To: Penny Zheng <Penny.Zheng@arm.com>; xen-devel@lists.xenproject.org > Cc: Wei Chen <Wei.Chen@arm.com>; Stefano Stabellini > <sstabellini@kernel.org>; Bertrand Marquis <Bertrand.Marquis@arm.com>; > Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> > Subject: Re: [PATCH v2 03/40] xen/arm: adjust Xen TLB helpers for Armv8- > R64 PMSA > > Hi, > > On 13/01/2023 05:28, Penny Zheng wrote: > > From: Wei Chen <wei.chen@arm.com> > > > > From Arm ARM Supplement of Armv8-R AArch64 (DDI 0600A) [1], > > section D1.6.2 TLB maintenance instructions, we know that > > Armv8-R AArch64 permits an implementation to cache stage 1 > > VMSAv8-64 and stage 2 PMSAv8-64 attributes as a common entry > > for the Secure EL1&0 translation regime. But for Xen itself, > > it's running with stage 1 PMSAv8-64 on Armv8-R AArch64. The > > EL2 MPU updates for stage 1 PMSAv8-64 will not be cached in > > TLB entries. So we don't need any TLB invalidation for Xen > > itself in EL2. > > So I understand the theory here. But I would expect that none of the > common code will call any of those helpers. Therefore the #ifdef should > be unnecessary. > > Can you clarify if my understanding is correct? > Yes, you're right, after we separate common code and MMU code, these helpers will be called in MMU specific code only. We will drop this patch in next version. Cheers, Wei Chen > Cheers, > > -- > Julien Grall
diff --git a/xen/arch/arm/include/asm/arm64/flushtlb.h b/xen/arch/arm/include/asm/arm64/flushtlb.h index 7c54315187..fe445f6831 100644 --- a/xen/arch/arm/include/asm/arm64/flushtlb.h +++ b/xen/arch/arm/include/asm/arm64/flushtlb.h @@ -51,6 +51,8 @@ TLB_HELPER(flush_all_guests_tlb_local, alle1); /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ TLB_HELPER(flush_all_guests_tlb, alle1is); +#ifndef CONFIG_HAS_MPU + /* Flush all hypervisor mappings from the TLB of the local processor. */ TLB_HELPER(flush_xen_tlb_local, alle2); @@ -66,6 +68,29 @@ static inline void __flush_xen_tlb_one(vaddr_t va) asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); } +#else + +/* + * When Xen is running with stage 1 PMSAv8-64 on MPU systems. The EL2 MPU + * updates for stage1 PMSAv8-64 will not be cached in TLB entries. So we + * don't need any TLB invalidation for Xen itself in EL2. See Arm ARM + * Supplement of Armv8-R AArch64 (DDI 0600A), section D1.6.2 TLB maintenance + * instructions for more details. + */ +static inline void flush_xen_tlb_local(void) +{ +} + +static inline void __flush_xen_tlb_one_local(vaddr_t va) +{ +} + +static inline void __flush_xen_tlb_one(vaddr_t va) +{ +} + +#endif /* CONFIG_HAS_MPU */ + #endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */ /* * Local variables: diff --git a/xen/arch/arm/include/asm/flushtlb.h b/xen/arch/arm/include/asm/flushtlb.h index 125a141975..4b8bf65281 100644 --- a/xen/arch/arm/include/asm/flushtlb.h +++ b/xen/arch/arm/include/asm/flushtlb.h @@ -28,6 +28,7 @@ static inline void page_set_tlbflush_timestamp(struct page_info *page) /* Flush specified CPUs' TLBs */ void arch_flush_tlb_mask(const cpumask_t *mask); +#ifndef CONFIG_HAS_MPU /* * Flush a range of VA's hypervisor mappings from the TLB of the local * processor. @@ -66,6 +67,27 @@ static inline void flush_xen_tlb_range_va(vaddr_t va, isb(); } +#else + +/* + * When Xen is running with stage 1 PMSAv8-64 on MPU systems. The EL2 MPU + * updates for stage1 PMSAv8-64 will not be cached in TLB entries. So we + * don't need any TLB invalidation for Xen itself in EL2. See Arm ARM + * Supplement of Armv8-R AArch64 (DDI 0600A), section D1.6.2 TLB maintenance + * instructions for more details. + */ +static inline void flush_xen_tlb_range_va_local(vaddr_t va, + unsigned long size) +{ +} + +static inline void flush_xen_tlb_range_va(vaddr_t va, + unsigned long size) +{ +} + +#endif /* CONFIG_HAS_MPU */ + #endif /* __ASM_ARM_FLUSHTLB_H__ */ /* * Local variables: