[v2,5.10.y-cip,00/44] Add support for Renesas RZ/Five RISC-V SoC

Message ID	20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
Headers	show Return-Path: <prabhakar.mahadev-lad.rj@bp.renesas.com> ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Biju Das <biju.das.jz@bp.renesas.com> Subject: [PATCH v2 5.10.y-cip 00/44] Add support for Renesas RZ/Five RISC-V SoC Date: Tue, 6 Feb 2024 12:26:50 +0000 Message-Id: <20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add support for Renesas RZ/Five RISC-V SoC \| expand [v2,5.10.y-cip,00/44] Add support for Renesas RZ/Five RISC-V SoC [v2,5.10.y-cip,01/44] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS [v2,5.10.y-cip,02/44] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS [v2,5.10.y-cip,03/44] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to speci… [v2,5.10.y-cip,04/44] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels [v2,5.10.y-cip,05/44] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts [v2,5.10.y-cip,06/44] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() [v2,5.10.y-cip,07/44] riscv: Kconfig: Enable cpufreq kconfig menu [v2,5.10.y-cip,08/44] dma-direct: add support for dma_coherent_default_memory [v2,5.10.y-cip,09/44] dma-mapping: allow using the global coherent pool for !ARM [v2,5.10.y-cip,10/44] dma-mapping: simplify dma_init_coherent_memory [v2,5.10.y-cip,11/44] dma-mapping: add a dma_init_global_coherent helper [v2,5.10.y-cip,12/44] dma-mapping: make the global coherent pool conditional [v2,5.10.y-cip,13/44] of: also handle dma-noncoherent in of_dma_is_coherent() [v2,5.10.y-cip,14/44] of/irq: Use interrupts-extended to find parent [v2,5.10.y-cip,15/44] irqchip/sifive-plic: Improve naming scheme for per context offsets [v2,5.10.y-cip,16/44] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode [v2,5.10.y-cip,17/44] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC [v2,5.10.y-cip,18/44] irqchip/sifive-plic: Make better use of the effective affinity mask [v2,5.10.y-cip,19/44] irqchip/sifive-plic: Separate the enable and mask operations [v2,5.10.y-cip,20/44] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC [v2,5.10.y-cip,21/44] clocksource/drivers/riscv: Increase the clock source rating [v2,5.10.y-cip,22/44] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback [v2,5.10.y-cip,23/44] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on AR… [v2,5.10.y-cip,24/44] dt-bindings: riscv: Sort the CPU core list alphabetically [v2,5.10.y-cip,25/44] dt-bindings: riscv: Add Andes AX45MP core to the list [v2,5.10.y-cip,26/44] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset De… [v2,5.10.y-cip,27/44] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for … [v2,5.10.y-cip,28/44] soc: renesas: Identify RZ/Five SoC [v2,5.10.y-cip,29/44] clk: renesas: r9a07g043: Add support for RZ/Five SoC [v2,5.10.y-cip,30/44] cache: Add L2 cache management for Andes AX45MP RISC-V core [v2,5.10.y-cip,31/44] cache: ax45mp_cache: Add non coherent support [v2,5.10.y-cip,32/44] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC [v2,5.10.y-cip,33/44] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option [v2,5.10.y-cip,34/44] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC [v2,5.10.y-cip,35/44] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK [v2,5.10.y-cip,36/44] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zone… [v2,5.10.y-cip,37/44] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C [v2,5.10.y-cip,38/44] riscv: dts: renesas: rzfive-smarc-som: Enable WDT [v2,5.10.y-cip,39/44] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes [v2,5.10.y-cip,40/44] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} [v2,5.10.y-cip,41/44] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node [v2,5.10.y-cip,42/44] riscv: dts: renesas: r9a07g043f: Add L2 cache node [v2,5.10.y-cip,43/44] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property [v2,5.10.y-cip,44/44] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly di…

Message ID

20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)

Headers

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH v2 5.10.y-cip 00/44] Add support for Renesas RZ/Five RISC-V
 SoC
Date: Tue,  6 Feb 2024 12:26:50 +0000
Message-Id: <20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

Add support for Renesas RZ/Five RISC-V SoC | expand

Message

Prabhakar Mahadev Lad Feb. 6, 2024, 12:26 p.m. UTC

Hi All,

This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
support for this SoC has already been added to 6.1-cip kernel.

v1->v2
- Dropped the first patches from [1] as they were already merged into CIP
- Rebased the patches on top of v5.10.209-cip44
- Had to manually apply changes for patch #10 and #12, rest of the patches
  are unchanged.
- Added Reviewed-by tag from Nobuhiro Iwamatsu for all the patches

RFC->v1
- Patch #35 updated according uptstream for easier maitainance.
  Rest of the patches have been unchanged.
- Merged RFC series [0] and preporatory series [1].
- Previous test run results can be found at [2].
- RISC-V Renesas defconfig file can be found at [3].

[0] https://patchwork.kernel.org/project/cip-dev/cover/20240130203346.94488-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://patchwork.kernel.org/project/cip-dev/cover/20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[2] https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1160504705
[3] https://gitlab.com/cip-project/cip-kernel/cip-kernel-config/-/blob/rzfive-5.10-cip/5.10.y-cip/riscv/renesas_defconfig?ref_type=heads

Cheers,
Prabhakar

Christoph Hellwig (5):
  dma-direct: add support for dma_coherent_default_memory
  dma-mapping: allow using the global coherent pool for !ARM
  dma-mapping: simplify dma_init_coherent_memory
  dma-mapping: add a dma_init_global_coherent helper
  dma-mapping: make the global coherent pool conditional

Conor Dooley (1):
  riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy
    node

Heiko Stuebner (1):
  of: also handle dma-noncoherent in of_dma_is_coherent()

Lad Prabhakar (30):
  arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to
    board DTS
  arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS
  arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
    to specify interrupt property
  arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
  arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
  riscv: Kconfig: Enable cpufreq kconfig menu
  irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
  clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC
  clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback
  mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option
    dependant on ARCH_RENESAS
  dt-bindings: riscv: Sort the CPU core list alphabetically
  dt-bindings: riscv: Add Andes AX45MP core to the list
  dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and
    Reset Definitions
  dt-bindings: cache: andestech,ax45mp-cache: Add DT binding
    documentation for L2 cache controller
  soc: renesas: Identify RZ/Five SoC
  clk: renesas: r9a07g043: Add support for RZ/Five SoC
  cache: Add L2 cache management for Andes AX45MP RISC-V core
  cache: ax45mp_cache: Add non coherent support
  soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
  riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
  riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
  riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
  riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable
    ADC/OPP/Thermal Zones/TSU
  riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
  riscv: dts: renesas: rzfive-smarc-som: Enable WDT
  riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes
  riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for
    ETH{0,1}
  riscv: dts: renesas: r9a07g043f: Add L2 cache node
  riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
  riscv: dts: renesas: rzfive-smarc: Enable the blocks which were
    explicitly disabled

Niklas Cassel (2):
  irqchip/sifive-plic: Improve naming scheme for per context offsets
  irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode

Samuel Holland (4):
  of/irq: Use interrupts-extended to find parent
  irqchip/sifive-plic: Make better use of the effective affinity mask
  irqchip/sifive-plic: Separate the enable and mask operations
  clocksource/drivers/riscv: Increase the clock source rating

Xiongfeng Wang (1):
  cacheinfo: clear cache_leaves(cpu) in free_cache_attributes()

 .../cache/andestech,ax45mp-cache.yaml         |  81 ++++
 .../devicetree/bindings/riscv/cpus.yaml       |   7 +-
 MAINTAINERS                                   |   7 +
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi    | 350 ++++++++----------
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi   |  72 ++++
 .../boot/dts/renesas/r9a07g043u11-smarc.dts   |  17 +-
 arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi |  14 -
 arch/riscv/Kconfig                            |   3 +-
 arch/riscv/Kconfig.socs                       |   5 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/renesas/Makefile          |   2 +
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi   |  72 ++++
 .../boot/dts/renesas/r9a07g043f01-smarc.dts   |  27 ++
 .../boot/dts/renesas/rzfive-smarc-som.dtsi    |  24 ++
 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi |   8 +
 arch/riscv/kernel/time.c                      |   9 -
 drivers/Kconfig                               |   2 +
 drivers/Makefile                              |   1 +
 drivers/base/cacheinfo.c                      |   1 +
 drivers/cache/Kconfig                         |  12 +
 drivers/cache/Makefile                        |   3 +
 drivers/cache/ax45mp_cache.c                  | 239 ++++++++++++
 drivers/clk/renesas/r9a07g043-cpg.c           |  32 ++
 drivers/clocksource/renesas-ostm.c            |   2 +-
 drivers/clocksource/timer-riscv.c             |   7 +-
 drivers/irqchip/Kconfig                       |   1 +
 drivers/irqchip/irq-sifive-plic.c             | 178 ++++++---
 drivers/mmc/host/Kconfig                      |   4 +-
 drivers/of/address.c                          |  17 +-
 drivers/of/irq.c                              |  13 +-
 drivers/soc/renesas/Kconfig                   |  12 +
 drivers/soc/renesas/renesas-soc.c             |  13 +
 include/dt-bindings/clock/r9a07g043-cpg.h     |  20 +
 include/linux/dma-map-ops.h                   |  18 +-
 kernel/dma/Kconfig                            |   4 +
 kernel/dma/coherent.c                         | 161 ++++----
 kernel/dma/direct.c                           |  17 +
 37 files changed, 1073 insertions(+), 383 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/Makefile
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
 create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/ax45mp_cache.c


base-commit: 27719b72779610a00d04c99a980d92fd02d256c2

Comments

Pavel Machek Feb. 6, 2024, 5:51 p.m. UTC | #1

Hi!

> This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> support for this SoC has already been added to 6.1-cip kernel.
> 
> v1->v2
> - Dropped the first patches from [1] as they were already merged into CIP
> - Rebased the patches on top of v5.10.209-cip44
> - Had to manually apply changes for patch #10 and #12, rest of the patches
>   are unchanged.
> - Added Reviewed-by tag from Nobuhiro Iwamatsu for all the patches

Thanks for the series. Patches #10 and #12 still look ok to me, it
passes the testing, and it already has Nobuhiro's reviewed-by tag. So
I went ahead and applied the series.

Looking forward to seeing risc-v renesas & qemu results in the gitlab!

Best regards,
								Pavel