diff mbox series

[v5,21/22] drm/i915/dg1: DG1 does not support DC6

Message ID 20200724213918.27424-22-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Introduce DG1 | expand

Commit Message

Lucas De Marchi July 24, 2020, 9:39 p.m. UTC 
From: Anshuman Gupta <anshuman.gupta@intel.com>

DC6 is not supported on DG1, so change the allowed DC mask for DG1.

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Souza, Jose Aug. 3, 2020, 11:33 p.m. UTC | #1 
On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> 
> DC6 is not supported on DG1, so change the allowed DC mask for DG1.
> 
> Cc: Uma Shankar <
> uma.shankar@intel.com
> >
> Signed-off-by: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 21f39c94056e..389a0f2d3a14 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
>  	int max_dc;
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		max_dc = 4;
> +		if (IS_DG1(dev_priv))

Better change to IS_DGFX() as DC6 is a SOC power-saving state, no discrete card will enter it.
With this change:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> +			max_dc = 3;
> +		else
> +			max_dc = 4;
>  		/*
>  		 * DC9 has a separate HW flow from the rest of the DC states,
>  		 * not depending on the DMC firmware. It's needed by system
>
Lucas De Marchi Aug. 24, 2020, 9:26 p.m. UTC | #2 
On Mon, Aug 03, 2020 at 04:33:45PM -0700, Jose Souza wrote:
>On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
>> From: Anshuman Gupta <
>> anshuman.gupta@intel.com
>> >
>>
>> DC6 is not supported on DG1, so change the allowed DC mask for DG1.
>>
>> Cc: Uma Shankar <
>> uma.shankar@intel.com
>> >
>> Signed-off-by: Anshuman Gupta <
>> anshuman.gupta@intel.com
>> >
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 21f39c94056e..389a0f2d3a14 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
>>  	int max_dc;
>>
>>  	if (INTEL_GEN(dev_priv) >= 12) {
>> -		max_dc = 4;
>> +		if (IS_DG1(dev_priv))
>
>Better change to IS_DGFX() as DC6 is a SOC power-saving state, no discrete card will enter it.
>With this change:

that doesn't seem true... it's more a dg1 thing than general dgfx

Lucas De Marchi

>Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
>> +			max_dc = 3;
>> +		else
>> +			max_dc = 4;
>>  		/*
>>  		 * DC9 has a separate HW flow from the rest of the DC states,
>>  		 * not depending on the DMC firmware. It's needed by system
>>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 21f39c94056e..389a0f2d3a14 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4689,7 +4689,10 @@  static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	int max_dc;
 
 	if (INTEL_GEN(dev_priv) >= 12) {
-		max_dc = 4;
+		if (IS_DG1(dev_priv))
+			max_dc = 3;
+		else
+			max_dc = 4;
 		/*
 		 * DC9 has a separate HW flow from the rest of the DC states,
 		 * not depending on the DMC firmware. It's needed by system