| Message ID | 20200724213918.27424-8-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce DG1 | expand |
On Fri, Jul 24, 2020 at 02:39:03PM -0700, Lucas De Marchi wrote: > From: Aditya Swarup <aditya.swarup@intel.com> > > Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks. > Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for > DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1. As on the previous patch, let's use the DG1 "DDI-TC1" and "DDI-TC2" terminology to avoid confusion (especially since the C/D here aren't even the same as the PORT_D/PORT_E that they index as in the driver). > > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 +++++++++++++++++-- > 1 file changed, 37 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index 81ab975fe4f0..39a53aa0b233 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -3512,7 +3512,17 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, > > icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); > > - if (IS_ROCKETLAKE(dev_priv)) { > + if (IS_DG1(dev_priv)) { > + if (port == PORT_D || port == PORT_E) { > + dpll_mask = > + BIT(DPLL_ID_DG1_DPLL2) | > + BIT(DPLL_ID_DG1_DPLL3); > + } else { > + dpll_mask = > + BIT(DPLL_ID_DG1_DPLL0) | > + BIT(DPLL_ID_DG1_DPLL1); > + } > + } else if (IS_ROCKETLAKE(dev_priv)) { > dpll_mask = > BIT(DPLL_ID_EHL_DPLL4) | > BIT(DPLL_ID_ICL_DPLL1) | > @@ -3808,7 +3818,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, > if (!(val & PLL_ENABLE)) > goto out; > > - if (IS_ROCKETLAKE(dev_priv)) { > + if (IS_DG1(dev_priv)) { > + hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); > + hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id)); > + } else if (IS_ROCKETLAKE(dev_priv)) { > hw_state->cfgcr0 = intel_de_read(dev_priv, > RKL_DPLL_CFGCR0(id)); > hw_state->cfgcr1 = intel_de_read(dev_priv, > @@ -3866,7 +3879,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, > const enum intel_dpll_id id = pll->info->id; > i915_reg_t cfgcr0_reg, cfgcr1_reg; > > - if (IS_ROCKETLAKE(dev_priv)) { > + if (IS_DG1(dev_priv)) { > + cfgcr0_reg = DG1_DPLL_CFGCR0(id); > + cfgcr1_reg = DG1_DPLL_CFGCR1(id); > + } else if (IS_ROCKETLAKE(dev_priv)) { > cfgcr0_reg = RKL_DPLL_CFGCR0(id); > cfgcr1_reg = RKL_DPLL_CFGCR1(id); > } else if (INTEL_GEN(dev_priv) >= 12) { > @@ -4316,6 +4332,21 @@ static const struct intel_dpll_mgr rkl_pll_mgr = { > .dump_hw_state = icl_dump_hw_state, > }; > > +static const struct dpll_info dg1_plls[] = { > + { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 }, > + { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 }, > + { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 }, > + { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 }, > + { }, > +}; > + > +static const struct intel_dpll_mgr dg1_pll_mgr = { > + .dpll_info = dg1_plls, > + .get_dplls = icl_get_dplls, > + .put_dplls = icl_put_dplls, > + .dump_hw_state = icl_dump_hw_state, Do we also need a .update_ref_clks = icl_update_dpll_ref_clks, here? That's a new hook as of ccc495fd7ac3 ("drm/i915: Unify the DPLL ref clock frequency tracking"). Matt > +}; > + > /** > * intel_shared_dpll_init - Initialize shared DPLLs > * @dev: drm device > @@ -4329,7 +4360,9 @@ void intel_shared_dpll_init(struct drm_device *dev) > const struct dpll_info *dpll_info; > int i; > > - if (IS_ROCKETLAKE(dev_priv)) > + if (IS_DG1(dev_priv)) > + dpll_mgr = &dg1_pll_mgr; > + else if (IS_ROCKETLAKE(dev_priv)) > dpll_mgr = &rkl_pll_mgr; > else if (INTEL_GEN(dev_priv) >= 12) > dpll_mgr = &tgl_pll_mgr; > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 81ab975fe4f0..39a53aa0b233 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3512,7 +3512,17 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); - if (IS_ROCKETLAKE(dev_priv)) { + if (IS_DG1(dev_priv)) { + if (port == PORT_D || port == PORT_E) { + dpll_mask = + BIT(DPLL_ID_DG1_DPLL2) | + BIT(DPLL_ID_DG1_DPLL3); + } else { + dpll_mask = + BIT(DPLL_ID_DG1_DPLL0) | + BIT(DPLL_ID_DG1_DPLL1); + } + } else if (IS_ROCKETLAKE(dev_priv)) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | @@ -3808,7 +3818,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, if (!(val & PLL_ENABLE)) goto out; - if (IS_ROCKETLAKE(dev_priv)) { + if (IS_DG1(dev_priv)) { + hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id)); + } else if (IS_ROCKETLAKE(dev_priv)) { hw_state->cfgcr0 = intel_de_read(dev_priv, RKL_DPLL_CFGCR0(id)); hw_state->cfgcr1 = intel_de_read(dev_priv, @@ -3866,7 +3879,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, const enum intel_dpll_id id = pll->info->id; i915_reg_t cfgcr0_reg, cfgcr1_reg; - if (IS_ROCKETLAKE(dev_priv)) { + if (IS_DG1(dev_priv)) { + cfgcr0_reg = DG1_DPLL_CFGCR0(id); + cfgcr1_reg = DG1_DPLL_CFGCR1(id); + } else if (IS_ROCKETLAKE(dev_priv)) { cfgcr0_reg = RKL_DPLL_CFGCR0(id); cfgcr1_reg = RKL_DPLL_CFGCR1(id); } else if (INTEL_GEN(dev_priv) >= 12) { @@ -4316,6 +4332,21 @@ static const struct intel_dpll_mgr rkl_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info dg1_plls[] = { + { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 }, + { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 }, + { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 }, + { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 }, + { }, +}; + +static const struct intel_dpll_mgr dg1_pll_mgr = { + .dpll_info = dg1_plls, + .get_dplls = icl_get_dplls, + .put_dplls = icl_put_dplls, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -4329,7 +4360,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (IS_ROCKETLAKE(dev_priv)) + if (IS_DG1(dev_priv)) + dpll_mgr = &dg1_pll_mgr; + else if (IS_ROCKETLAKE(dev_priv)) dpll_mgr = &rkl_pll_mgr; else if (INTEL_GEN(dev_priv) >= 12) dpll_mgr = &tgl_pll_mgr;