| Message ID | 20200724213918.27424-5-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce DG1 | expand |
On Fri, Jul 24, 2020 at 02:39:00PM -0700, Lucas De Marchi wrote: > From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com> > > On dgfx register range has been extended to go up to 4MB. > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Michael J. Ruhl <michael.j.ruhl@intel.com> > Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> We may want to provide "Bspec: 53616" as a reference. Technically the overall space reserved for MMIO is 8MB, but that page helps detail the layout. The registers we actually use top out out 28_0000 I believe, so a 4MB range should be sufficient. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/intel_uncore.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index f5edee17902a..8f9c82aa7338 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1701,11 +1701,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore) > * clobbering the GTT which we want ioremap_wc instead. Fortunately, > * the register BAR remains the same size for all the earlier > * generations up to Ironlake. > + * For dgfx chips register range is expanded to 4MB. > */ > if (INTEL_GEN(i915) < 5) > mmio_size = 512 * 1024; > + else if (IS_DGFX(i915)) > + mmio_size = 4 * 1024 * 1024; > else > mmio_size = 2 * 1024 * 1024; > + > uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); > if (uncore->regs == NULL) { > drm_err(&i915->drm, "failed to map registers\n"); > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index f5edee17902a..8f9c82aa7338 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1701,11 +1701,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore) * clobbering the GTT which we want ioremap_wc instead. Fortunately, * the register BAR remains the same size for all the earlier * generations up to Ironlake. + * For dgfx chips register range is expanded to 4MB. */ if (INTEL_GEN(i915) < 5) mmio_size = 512 * 1024; + else if (IS_DGFX(i915)) + mmio_size = 4 * 1024 * 1024; else mmio_size = 2 * 1024 * 1024; + uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); if (uncore->regs == NULL) { drm_err(&i915->drm, "failed to map registers\n");