diff mbox series

[37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane

Message ID 20230823170740.1180212-38-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Enable Lunar Lake display | expand

Commit Message

Lucas De Marchi Aug. 23, 2023, 5:07 p.m. UTC
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Previously we always updated DBuf MBUS CTL and DBUF CTL regs after
CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like
that anymore. According to BSpec, we have to first update DBuf regs and
then write CDCLK regs, when CDCLK is decreased, which we do in post
plane.

So now we do CDCLK post plane update only after DBuf regs are
written (CDCLK/MDCLK separation requires MDCLK/CDCLK ratio to be written
to DBuf regs).

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Mika Kahola Aug. 25, 2023, 7:35 a.m. UTC | #1
> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Wednesday, August 23, 2023 8:08 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>; Kahola, Mika <mika.kahola@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
> 
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> Previously we always updated DBuf MBUS CTL and DBUF CTL regs after CDCLK has been changed(CDCLK_CTL), however for Xe2-
> LPD we can't do like that anymore. According to BSpec, we have to first update DBuf regs and then write CDCLK regs, when CDCLK
> is decreased, which we do in post plane.
> 
> So now we do CDCLK post plane update only after DBuf regs are written (CDCLK/MDCLK separation requires MDCLK/CDCLK ratio
> to be written to DBuf regs).
> 
> Cc: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f9eda7ad892e..de813831a5cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7113,7 +7113,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>  	dev_priv->display.funcs.display->commit_modeset_enables(state);
> 
> -	if (state->modeset)
> +	if (state->modeset && DISPLAY_VER(dev_priv) < 20)
>  		intel_set_cdclk_post_plane_update(state);
> 
>  	intel_wait_for_vblank_workers(state);
> @@ -7160,6 +7160,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	intel_dbuf_post_plane_update(state);
>  	intel_psr_post_plane_update(state);
> 
> +	if (state->modeset && DISPLAY_VER(dev_priv) >= 20)
> +		intel_set_cdclk_post_plane_update(state);
> +
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>  		intel_post_plane_update(state, crtc);
> 
> --
> 2.40.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f9eda7ad892e..de813831a5cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7113,7 +7113,7 @@  static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	dev_priv->display.funcs.display->commit_modeset_enables(state);
 
-	if (state->modeset)
+	if (state->modeset && DISPLAY_VER(dev_priv) < 20)
 		intel_set_cdclk_post_plane_update(state);
 
 	intel_wait_for_vblank_workers(state);
@@ -7160,6 +7160,9 @@  static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	intel_dbuf_post_plane_update(state);
 	intel_psr_post_plane_update(state);
 
+	if (state->modeset && DISPLAY_VER(dev_priv) >= 20)
+		intel_set_cdclk_post_plane_update(state);
+
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 		intel_post_plane_update(state, crtc);