| Message ID | 20230823170740.1180212-39-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable Lunar Lake display | expand |
On Wed, Aug 23, 2023 at 10:07:36AM -0700, Lucas De Marchi wrote: >From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > >mdclk_cdclk_ratio is a part of dbuf_state and if it changes, it requires >hw to be poked, so we must serialize the global state in that case. > >Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> >Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> >--- > drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++++++++++++---- > 1 file changed, 15 insertions(+), 4 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c >index 4d8b960389ec..38a9c47e4ae1 100644 >--- a/drivers/gpu/drm/i915/display/intel_cdclk.c >+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c >@@ -2789,7 +2789,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > struct intel_crtc_state *crtc_state; > int min_cdclk, i; > enum pipe pipe; >- struct intel_dbuf_state *dbuf_state; >+ struct intel_dbuf_state *new_dbuf_state; >+ struct intel_dbuf_state *old_dbuf_state; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > int ret; >@@ -2823,11 +2824,21 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > } > } > >- dbuf_state = intel_atomic_get_new_dbuf_state(state); >- if (dbuf_state) >- dbuf_state->mdclk_cdclk_ratio = >+ new_dbuf_state = intel_atomic_get_new_dbuf_state(state); >+ old_dbuf_state = intel_atomic_get_old_dbuf_state(state); humn... it looks like this should actually be squashed in one of the previous patches that added this. Lucas De Marchi >+ if (new_dbuf_state && old_dbuf_state) { >+ new_dbuf_state->mdclk_cdclk_ratio = > get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual); > >+ if (new_dbuf_state->mdclk_cdclk_ratio != old_dbuf_state->mdclk_cdclk_ratio) { >+ int ret; >+ >+ ret = intel_atomic_serialize_global_state(&new_dbuf_state->base); >+ if (ret) >+ return ret; >+ } >+ } >+ > min_cdclk = max(cdclk_state->force_min_cdclk, > cdclk_state->bw_min_cdclk); > for_each_pipe(dev_priv, pipe) >-- >2.40.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 4d8b960389ec..38a9c47e4ae1 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2789,7 +2789,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) struct intel_crtc_state *crtc_state; int min_cdclk, i; enum pipe pipe; - struct intel_dbuf_state *dbuf_state; + struct intel_dbuf_state *new_dbuf_state; + struct intel_dbuf_state *old_dbuf_state; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { int ret; @@ -2823,11 +2824,21 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) } } - dbuf_state = intel_atomic_get_new_dbuf_state(state); - if (dbuf_state) - dbuf_state->mdclk_cdclk_ratio = + new_dbuf_state = intel_atomic_get_new_dbuf_state(state); + old_dbuf_state = intel_atomic_get_old_dbuf_state(state); + if (new_dbuf_state && old_dbuf_state) { + new_dbuf_state->mdclk_cdclk_ratio = get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual); + if (new_dbuf_state->mdclk_cdclk_ratio != old_dbuf_state->mdclk_cdclk_ratio) { + int ret; + + ret = intel_atomic_serialize_global_state(&new_dbuf_state->base); + if (ret) + return ret; + } + } + min_cdclk = max(cdclk_state->force_min_cdclk, cdclk_state->bw_min_cdclk); for_each_pipe(dev_priv, pipe)