diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index d9434cd0f568..b5ad6798978c 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -25,6 +25,18 @@ .align 5 NESTED(handle_sys, PT_SIZE, sp) .set noat +#ifdef CONFIG_CPU_R5900 + /* + * We don't want to stumble over broken sign extensions from + * userland. O32 does never use the upper half, but since the + * R5900 does not implement CP0.Status.UX it cannot enforce it. + */ + sll v0, v0, 0 + sll a0, a0, 0 + sll a1, a1, 0 + sll a2, a2, 0 + sll a3, a3, 0 +#endif SAVE_SOME TRACE_IRQS_ON_RELOAD STI
The R5900 has 64-bit instructions but does not implement CP0.Status.UX so a 32-bit kernel cannot assume o32 registers are sign-extended[1]. CP0.Status.{UX,SX,KX} are read-only and always read as zero. CP0.Status.PX (bit 23) is called CP0.Status.DEV and controls the location of performance counter and debug/SIO exception vectors. In other MIPS ISA implementations, attempting to execute 64-bit operations in 32-bit user or supervisor mode may cause the reserved instruction exception. In the Emotion Engine core, however, 64-bit operations are always valid, regardless of the operation mode[2]. References: [1] "TX System RISC TX79 Core Architecture" manual, revision 2.0, Toshiba Corporation, p. 4-16, https://wiki.qemu.org/File:C790.pdf [2] "EE Core User's Manual", version 6.0, Sony Computer Entertainment Inc., p. 107. Signed-off-by: Fredrik Noring <noring@nocrew.org> --- arch/mips/kernel/scall32-o32.S | 12 ++++++++++++ 1 file changed, 12 insertions(+)