diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 0519e2eafbb8..89ff0eae5397 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -622,6 +622,15 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l, uasm_i_nop(p); tlbw(p); break; + case CPU_R5900: + /* + * On the R5900, the TLBWI and TLBWR instructions must be + * followed by an ERET or a SYNC.P instruction to ensure a + * TLB update. + */ + tlbw(p); + uasm_i_syncp(p); + break; case CPU_JZRISC: tlbw(p);
On the R5900, the TLBWI[1] and TLBWR[2] instructions must be followed by an ERET or a SYNC.P instruction to ensure a TLB update. References: [1] "TX System RISC TX79 Core Architecture" manual, revision 2.0, Toshiba Corporation, p. C-39, https://wiki.qemu.org/File:C790.pdf [2] Ibid. p. C-40. Signed-off-by: Fredrik Noring <noring@nocrew.org> --- arch/mips/mm/tlbex.c | 9 +++++++++ 1 file changed, 9 insertions(+)