[024/120] MIPS: PS2: Define PlayStation 2 I/O port, ROM and RAM address spaces

Commit Message

Fredrik Noring Sept. 1, 2019, 3:46 p.m. UTC

Signed-off-by: Fredrik Noring <[e-mail]>
---
 arch/mips/include/asm/mach-ps2/rom.h | 17 +++++++++++++++++
 arch/mips/ps2/Makefile               |  1 +
 arch/mips/ps2/memory.c               | 27 +++++++++++++++++++++++++++
 3 files changed, 45 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-ps2/rom.h
 create mode 100644 arch/mips/ps2/Makefile
 create mode 100644 arch/mips/ps2/memory.c

Patch

diff --git a/arch/mips/include/asm/mach-ps2/rom.h b/arch/mips/include/asm/mach-ps2/rom.h
new file mode 100644
index 000000000000..6760be183696
--- /dev/null
+++ b/arch/mips/include/asm/mach-ps2/rom.h
@@ -0,0 +1,17 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PlayStation 2 read-only memory (ROM)
+ *
+ * Copyright (C) 2019 Fredrik Noring
+ */
+
+#ifndef __ASM_MACH_PS2_ROM_H
+#define __ASM_MACH_PS2_ROM_H
+
+#define ROM0_BASE	0x1fc00000	/* ROM0 base address (boot) */
+#define ROM0_SIZE	0x400000	/* ROM0 maximum size */
+
+#define ROM1_BASE	0x1e000000	/* ROM1 base address (DVD) */
+#define ROM1_SIZE	0x100000	/* ROM1 maximum size */
+
+#endif /* __ASM_MACH_PS2_ROM_H */
diff --git a/arch/mips/ps2/Makefile b/arch/mips/ps2/Makefile
new file mode 100644
index 000000000000..24d537d2fb9f
--- /dev/null
+++ b/arch/mips/ps2/Makefile
@@ -0,0 +1 @@ 
+obj-y		+= memory.o
diff --git a/arch/mips/ps2/memory.c b/arch/mips/ps2/memory.c
new file mode 100644
index 000000000000..66ca37f38330
--- /dev/null
+++ b/arch/mips/ps2/memory.c
@@ -0,0 +1,27 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PlayStation 2 memory
+ *
+ * Copyright (C) 2019 Fredrik Noring
+ */
+
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/types.h>
+
+#include <asm/bootinfo.h>
+
+void __init plat_mem_setup(void)
+{
+	ioport_resource.start = 0x10000000;
+	ioport_resource.end   = 0x1fffffff;
+
+	iomem_resource.start = 0x00000000;
+	iomem_resource.end   = KSEG2 - 1;
+
+	add_memory_region(0x00000000, 0x02000000, BOOT_MEM_RAM);
+	add_memory_region(ROM0_BASE, ROM0_SIZE, BOOT_MEM_ROM_DATA);
+	add_memory_region(ROM1_BASE, ROM1_SIZE, BOOT_MEM_ROM_DATA);
+
+	set_io_port_base(CKSEG1);	/* KSEG1 is uncached */
+}