@@ -34,6 +34,17 @@
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
+#ifdef CONFIG_CPU_R5900
+#define Index_Invalidate_I 0x07
+#define Index_Writeback_Inv_D 0x14
+#define Index_Load_Tag_I 0x00
+#define Index_Load_Tag_D 0x10
+#define Index_Store_Tag_I 0x04
+#define Index_Store_Tag_D 0x12
+#define Hit_Invalidate_I 0x0b
+#define Hit_Invalidate_D 0x1a
+#define Hit_Writeback_Inv_D 0x18
+#else
#define Index_Invalidate_I (Cache_I | Index_Writeback_Inv)
#define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv)
#define Index_Load_Tag_I (Cache_I | Index_Load_Tag)
@@ -43,14 +54,20 @@
#define Hit_Invalidate_I (Cache_I | Hit_Invalidate)
#define Hit_Invalidate_D (Cache_D | Hit_Invalidate)
#define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv)
+#endif
/*
* R4000-specific cacheops
*/
#define Create_Dirty_Excl_D (Cache_D | 0x0c)
+#ifdef CONFIG_CPU_R5900
+#define Fill 0x0e
+#define Hit_Writeback_D 0x1c
+#else
#define Fill (Cache_I | 0x14)
#define Hit_Writeback_I (Cache_I | Hit_Writeback)
#define Hit_Writeback_D (Cache_D | Hit_Writeback)
+#endif
/*
* R4000SC and R4400SC-specific cacheops
The CACHE instruction operation field encodings are listed in the TX79 manual[1]: Table C-1. CACHE Instruction Op Field Encoding Mnemonic | OpCode | CACHE Instruction | Target ---------+--------+------------------------------+------------------ IXIN | 00111 | INDEX INVALIDATE | Instruction Cache IXLTG | 00000 | INDEX LOAD TAG | Instruction Cache IXSTG | 00100 | INDEX STORE TAG | Instruction Cache IHIN | 01011 | HIT INVALIDATE | Instruction Cache IFL | 01110 | FILL | Instruction Cache IXLDT | 00001 | INDEX LOAD DATA | Instruction Cache IXSDT | 00101 | INDEX STORE DATA | Instruction Cache ---------+--------+------------------------------+------------------ BXLBT | 00010 | INDEX LOAD BTACC | BTAC BXSBT | 00110 | INDEX STORE BTAC | BTAC BFH | 01100 | BTAC FLUSH | BTAC BHINBT | 01010 | HIT INVALIDATE BTAC | BTAC ---------+--------+------------------------------+------------------ DXWBIN | 10100 | INDEX WRITE BACK INVALIDATE | Data Cache DXLTG | 10000 | INDEX LOAD TAG | Data Cache DXSTG | 10010 | INDEX STORE TAG | Data Cache DXIN | 10110 | INDEX INVALIDATE | Data Cache DHIN | 11010 | HIT INVALIDATE | Data Cache DHWBIN | 11000 | HIT WRITEBACK INVALIDATE | Data Cache DXLDT | 10001 | INDEX LOAD DATA | Data Cache DXSDT | 10011 | INDEX STORE DATA | Data Cache DHWOIN | 11100 | HIT WRITEBACK W/O INVALIDATE | Data Cache ---------+--------+------------------------------+------------------ References: [1] "TX System RISC TX79 Core Architecture" manual, revision 2.0, Toshiba Corporation, p. C-6, https://wiki.qemu.org/File:C790.pdf Signed-off-by: Fredrik Noring <noring@nocrew.org> --- arch/mips/include/asm/cacheops.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)