| Message ID | 20190830134515.11925-6-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 8a6d97a46dfd73a87b76a277b2045bd4036c35aa |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | clk: renesas: rcar-gen2/gen3: Switch to .determine_rate() | expand |
Hi Geert, Thanks for your patch. On 2019-08-30 15:45:12 +0200, Geert Uytterhoeven wrote: > cpg_sd_clock_round_rate() really needs the best rate, not the best > divider. Hence change the iteration to find the former, and get rid of > the final division. > > Add an out-of-range rate check while at it. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > v2: > - Split off from "clk: renesas: rcar-gen3: Switch SD clocks to > .determine_rate()". > --- > drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c > index 12ea5c9a671de788..a612045cba7d97b7 100644 > --- a/drivers/clk/renesas/rcar-gen3-cpg.c > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c > @@ -312,21 +312,25 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, > static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, > unsigned long *parent_rate) > { > - unsigned long calc_rate, diff, diff_min = ULONG_MAX; > + unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX; > struct sd_clock *clock = to_sd_clock(hw); > - unsigned int i, best_div = 0; > + unsigned long calc_rate, diff; > + unsigned int i; > > for (i = 0; i < clock->div_num; i++) { > calc_rate = DIV_ROUND_CLOSEST(*parent_rate, > clock->div_table[i].div); > diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate; > if (diff < diff_min) { > - best_div = clock->div_table[i].div; > + best_rate = calc_rate; > diff_min = diff; > } > } > > - return DIV_ROUND_CLOSEST(*parent_rate, best_div); > + if (best_rate > LONG_MAX) > + return -EINVAL; > + > + return best_rate; > } > > static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, > -- > 2.17.1 >
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 12ea5c9a671de788..a612045cba7d97b7 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -312,21 +312,25 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - unsigned long calc_rate, diff, diff_min = ULONG_MAX; + unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX; struct sd_clock *clock = to_sd_clock(hw); - unsigned int i, best_div = 0; + unsigned long calc_rate, diff; + unsigned int i; for (i = 0; i < clock->div_num; i++) { calc_rate = DIV_ROUND_CLOSEST(*parent_rate, clock->div_table[i].div); diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate; if (diff < diff_min) { - best_div = clock->div_table[i].div; + best_rate = calc_rate; diff_min = diff; } } - return DIV_ROUND_CLOSEST(*parent_rate, best_div); + if (best_rate > LONG_MAX) + return -EINVAL; + + return best_rate; } static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
cpg_sd_clock_round_rate() really needs the best rate, not the best divider. Hence change the iteration to find the former, and get rid of the final division. Add an out-of-range rate check while at it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2: - Split off from "clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()". --- drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)